{"id":29393,"created":"2025-01-18T22:59:15.302823+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00029393","sets":["1164:2240:2278:2282"]},"path":["2282"],"owner":"1","recid":"29393","title":["マルチスレッドプロセッサにおけるメモリアクセスレイテンシ隠蔽の一手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2001-03-08"},"_buckets":{"deposit":"cc8970dc-ed59-4192-b04e-e8e4079b52c4"},"_deposit":{"id":"29393","pid":{"type":"depid","value":"29393","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"マルチスレッドプロセッサにおけるメモリアクセスレイテンシ隠蔽の一手法","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"マルチスレッドプロセッサにおけるメモリアクセスレイテンシ隠蔽の一手法"},{"subitem_title":"A technique of hiding memory access latency for Multi - threading Processor","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2001-03-08","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"九州大学大学院システム情報科学府"},{"subitem_text_value":"九州大学大学院システム情報科学研究院"},{"subitem_text_value":"九州大学大学院システム情報科学研究院"},{"subitem_text_value":"九州大学大学院システム情報科学研究院"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information Science and Electrical Engineering, Kyushu University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science and Electrical Engineering, Kyushu University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science and Electrical Engineering, Kyushu University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science and Electrical Engineering, Kyushu University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/29393/files/IPSJ-HPC00085012.pdf"},"date":[{"dateType":"Available","dateValue":"2003-03-08"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-HPC00085012.pdf","filesize":[{"value":"517.8 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"14"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"26f76daf-c996-4a86-92fa-1b90314a9f83","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2001 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"松崎, 隆哲"},{"creatorName":"富安, 洋史"},{"creatorName":"大庭, 直行"},{"creatorName":"雨宮, 真人"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Takanori, Matsuzaki","creatorNameLang":"en"},{"creatorName":"Hiroshi, Tomiyasu","creatorNameLang":"en"},{"creatorName":"Naoyuki, Ohba","creatorNameLang":"en"},{"creatorName":"Makoto, Amamiya","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10463942","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本稿では、マルチスレッドプロセッサにおけるメモリアクセスレイテンシの隠蔽の一手法について述べる。筆者らは複数のスレッド実行ユニットとメモリを一つのチップに搭載したFUCEプロセッサを提案している。FUCEプロセッサは、オンチップメモリを利用することでレイテンシの小さいメモリアクセスを実現する。また、スレッド先読み機構とプリロード機構を利用することで、メモリアクセスレイテンシの隠蔽を実現する。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"On this paper, we describe a technique of hiding memory access latency for multi-threading processor. So, we evaluate performances of the memory access latency with the model of FUCE processor. FUCE processor achieves low latency memory access with on-chip memory. Also, FUCE processor achieves hiding memory access latency by the thread context pre-fetch technique and the pre-load technique. Thus, FUCE processor can achieve thread-execution without the memory latency.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"72","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告ハイパフォーマンスコンピューティング（HPC）"}],"bibliographicPageStart":"67","bibliographicIssueDates":{"bibliographicIssueDate":"2001-03-08","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"22(2000-HPC-085)","bibliographicVolumeNumber":"2001"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"updated":"2025-01-22T17:34:24.934717+00:00","links":{}}