{"id":29388,"updated":"2025-01-22T17:34:16.228593+00:00","links":{},"created":"2025-01-18T22:59:15.080142+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00029388","sets":["1164:2240:2278:2282"]},"path":["2282"],"owner":"1","recid":"29388","title":["同期通信用メモリに対する並列化手法と評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"2001-03-08"},"_buckets":{"deposit":"c8a74463-4ae3-46a1-bd18-33fa0ae84998"},"_deposit":{"id":"29388","pid":{"type":"depid","value":"29388","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"同期通信用メモリに対する並列化手法と評価","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"同期通信用メモリに対する並列化手法と評価"},{"subitem_title":"A Parallelizing Method and Evaluation of The Communication and Synchronization Memory","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2001-03-08","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"九州工業大学工学部電気工学科"},{"subitem_text_value":"九州工業大学工学部電気工学科"},{"subitem_text_value":"九州工業大学工学部電気工学科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Depertment of Electronic Engineering, Faculty of Engineering, Kyushu Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Depertment of Electronic Engineering, Faculty of Engineering, Kyushu Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Depertment of Electronic Engineering, Faculty of Engineering, Kyushu Institute of Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/29388/files/IPSJ-HPC00085007.pdf"},"date":[{"dateType":"Available","dateValue":"2003-03-08"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-HPC00085007.pdf","filesize":[{"value":"739.6 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"14"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"a4388292-20a4-4e05-a67c-a870123143aa","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2001 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"山脇, 彰"},{"creatorName":"田中, 誠"},{"creatorName":"岩根, 雅彦"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Akira, Yamawaki","creatorNameLang":"en"},{"creatorName":"Makoto, Tanaka","creatorNameLang":"en"},{"creatorName":"Masahiko, Iwane","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10463942","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"半導体の集積度向上により，様々なマイクロプロセッサアーキテクチャが実現可能となっている．その選択肢の一つに複数のプロセッサコアを1チップに搭載したシングルチップマルチプロセッサ(SCMP)がある．SCMPはプログラムのスレッドレベルから命令レベルの並列性を抽出し性能向上を遂げるマルチスレッド実行環境を対象としている．そのような環境におけるスレッド間の先行制約を満たす機構として，タスクに属するスレッド間の高速な1対多の条件同期，相互排除およびバリア同期を実現できる同期通信用メモリTCSMIIがある．TCSMIIは無効なエントリに対する読み出しブロックを行うため，データの真依存に関してTCSMIIによる通信で先行制約を満たすことができる．TCSMIIはレジスタを介してアクセスされることから並列化の際にレジスタ変数を導入し，生産文と消費文を分割し，TCSMII命令を挿入する．並列化したプログラムの実行時間をSCMPと等価なマルチチップ・マルチプロセッサMTA/TCSMIIで実測した．結果より，逐次プログラムの実行時間に対して平均1.16?2.23の速度向上を得たことからTCSMIIの有効性が確認できた．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"The progress of semiconductor technology has made processors mounted on a single chip. the Single Chip-MultiProcessor(SCMP) extracts multiple threads and instruction parallelism across them from the application. In multithreading environment, it is an important problem how the interthread dependence is satisfied. TCSMII is a communication and synchronization memory that achieves a high-speed condition synchronization, mutual exclusion, and barrier synchronization between threads. TCSMII performs blocking to the consumer thread when it read a invalid data that is not written by the producer thread yet. Therefore, TCSMII satisfies the ture dependence between a consumer thread and the producer thread. Since TCSMII is accessed using a register, the register variable is used for inserting the instraction of TCSMII. we evaluate the parallelizing programs using TCSMII on MTA/TCSMII. The result shows that TCSMII achieves 1.16縲鰀2.23 speed-up on an average to the serial programs.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"42","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告ハイパフォーマンスコンピューティング（HPC）"}],"bibliographicPageStart":"37","bibliographicIssueDates":{"bibliographicIssueDate":"2001-03-08","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"22(2000-HPC-085)","bibliographicVolumeNumber":"2001"}]},"relation_version_is_last":true,"weko_creator_id":"1"}}