{"created":"2025-01-18T22:59:14.860030+00:00","updated":"2025-01-22T17:34:07.723818+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00029383","sets":["1164:2240:2278:2282"]},"path":["2282"],"owner":"1","recid":"29383","title":["大容量FPGAの応用によるマルチプロセッサエミュレーションシステムの開発"],"pubdate":{"attribute_name":"公開日","attribute_value":"2001-03-08"},"_buckets":{"deposit":"041f184b-54e7-486e-89e8-9b33c12414e2"},"_deposit":{"id":"29383","pid":{"type":"depid","value":"29383","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"大容量FPGAの応用によるマルチプロセッサエミュレーションシステムの開発","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"大容量FPGAの応用によるマルチプロセッサエミュレーションシステムの開発"},{"subitem_title":"Development of a Multiprocessor Emulation System by the Application of Large - scale FPGA","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2001-03-08","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"科学技術振興事業団"},{"subitem_text_value":"株式会社カーネル"},{"subitem_text_value":"電子技術総合研究所情報アーキテクチャ部"},{"subitem_text_value":"電子技術総合研究所情報アーキテクチャ部"},{"subitem_text_value":"電子技術総合研究所情報アーキテクチャ部／電気通信大学大学院情報システム学研究科"},{"subitem_text_value":"株式会社創夢"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Domestic Research Fellow, Japan Science and Technology Corporation","subitem_text_language":"en"},{"subitem_text_value":"Kernel Co., Ltd.","subitem_text_language":"en"},{"subitem_text_value":"Computer Science Division, Electrotechnical Laboratory","subitem_text_language":"en"},{"subitem_text_value":"Computer Science Division, Electrotechnical Laboratory","subitem_text_language":"en"},{"subitem_text_value":"Computer Science Division, Electrotechnical Laboratory/Graduate School of Information Systems, The University of Electro - Communications","subitem_text_language":"en"},{"subitem_text_value":"SOUM Corporation","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/29383/files/IPSJ-HPC00085002.pdf"},"date":[{"dateType":"Available","dateValue":"2003-03-08"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-HPC00085002.pdf","filesize":[{"value":"1.0 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"14"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"af0f621d-93f7-495d-af42-a2ab2619014e","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2001 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"佐谷野, 健二"},{"creatorName":"片下, 敏宏"},{"creatorName":"小池, 汎平"},{"creatorName":"児玉, 祐悦"},{"creatorName":"坂根, 広史"},{"creatorName":"甲村, 康人"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Kenji, Sayano","creatorNameLang":"en"},{"creatorName":"Toshihiro, Katashita","creatorNameLang":"en"},{"creatorName":"Hanpei, Koike","creatorNameLang":"en"},{"creatorName":"Yuetsu, Kodama","creatorNameLang":"en"},{"creatorName":"Hirofumi, Sakane","creatorNameLang":"en"},{"creatorName":"Yasuhito, Koumura","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10463942","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本研究では，近年大容量化の進むFPGAを応用してマルチプロセッサ向けエミュレーションシステムの開発を行っている．本システムでは，プロセッサコアとネットワーク機能を単一のFPGAチップ内に実装することで，高速なエミュレーション動作と高い柔軟性を実現する．また，FPGAチップ間を高速な差動信号バスで結ぶことにより，マルチプロセッサのエミュレーションを行う際のシステム全体の性能を考慮して設計を行った．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In this research, we are developing a multiprocessor emulation system by the application of large-scale FPGA that the capacity is increasing rapidly in recent years. This system realizes very high-speed emulation and high flexibility, since processor cores and network switches are implemented in a single FPGA chip. Furthermore, the system performance at multiprocessor emulation is regarded in the development of this system by that the high-speed differential I/O buses connect each FPGA chip.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"12","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告ハイパフォーマンスコンピューティング（HPC）"}],"bibliographicPageStart":"7","bibliographicIssueDates":{"bibliographicIssueDate":"2001-03-08","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"22(2000-HPC-085)","bibliographicVolumeNumber":"2001"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":29383,"links":{}}