{"links":{},"id":29116,"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00029116","sets":["1164:2240:2263:2266"]},"path":["2266"],"owner":"1","recid":"29116","title":["仮想キューマシンVQMの構成と基本性能評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"2004-04-13"},"_buckets":{"deposit":"1ba6d186-de27-4870-ac27-a11771cc21a6"},"_deposit":{"id":"29116","pid":{"type":"depid","value":"29116","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"仮想キューマシンVQMの構成と基本性能評価","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"仮想キューマシンVQMの構成と基本性能評価"},{"subitem_title":"Construction and Basic Performance Evaluation of Virtual Queue Machine","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2004-04-13","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京大学大学院新領域創成科学研究科基盤情報学専攻"},{"subitem_text_value":"電気通信大学大学院情報システム学研究科情報ネットワーク学専攻"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"The University of Tokyo, Graduate School of Frontier Sciences, Department of Frontier Informatics","subitem_text_language":"en"},{"subitem_text_value":"The University of Electro - Communications, Graduate School of Information Systems, Department of Information Network Science","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/29116/files/IPSJ-HPC04098006.pdf"},"date":[{"dateType":"Available","dateValue":"2006-04-13"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-HPC04098006.pdf","filesize":[{"value":"189.1 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"14"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"82e5b55c-80fa-4549-8012-a235147fbe8c","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2004 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"川田, 宗太郎"},{"creatorName":"曽和, 将容"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Sotaro, Kawata","creatorNameLang":"en"},{"creatorName":"Masahiro, Sowa","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10463942","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"キュー計算モデルに基づく新しい並列プロセッサ「キューマシン」に、仮想的にキューを長くする「仮想キュー」を導入することを提案する。このプロセッサは、仮想レジスタの導入によってプログラムサイズが小さいまま大並列実行が可能である。スーパスカラプロセッサとしてシステムを設計し、シミュレーションによって基本的な性能評価を行った。その結果、プロセス切り替えの効率が良く、プログラムサイズを考慮するとパフォーマンスが上がることが分かった。これは限られたハードウェア資源を有効に使うプロセッサである。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In this paper we propose a novel parallel processor, named Queue Machine, based on the queue calculation model. A \"Virtual Queue\" is introduced so that the queue length becomes virtually unlimited. Parallel processing can be easily performed by the proposed machine with the introduction of virtual registers while keeping small program size. We design the system as a super scalar processor and evaluate its basic performance. The results show that the processor decreases the process switching costs. In addition, programs for the proposed machine are considerably compact. Moreover, the processor makes good use of the limited hardware resources.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"36","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告ハイパフォーマンスコンピューティング（HPC）"}],"bibliographicPageStart":"31","bibliographicIssueDates":{"bibliographicIssueDate":"2004-04-13","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"38(2004-HPC-098)","bibliographicVolumeNumber":"2004"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"created":"2025-01-18T22:59:03.111146+00:00","updated":"2025-01-22T17:43:38.115361+00:00"}