{"updated":"2025-01-22T17:53:41.190413+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00028852","sets":["1164:2240:2247:2252"]},"path":["2252"],"owner":"1","recid":"28852","title":["Cellプロセッサの分岐ペナルティを軽減するソフトウェア分岐予測の可能性検討"],"pubdate":{"attribute_name":"公開日","attribute_value":"2007-03-02"},"_buckets":{"deposit":"a07f1d35-a9e4-4138-acb8-1b656176decc"},"_deposit":{"id":"28852","pid":{"type":"depid","value":"28852","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"Cellプロセッサの分岐ペナルティを軽減するソフトウェア分岐予測の可能性検討","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Cellプロセッサの分岐ペナルティを軽減するソフトウェア分岐予測の可能性検討"},{"subitem_title":"A software branch prediction to reduce the branch penalty of the Cell Broadband Engine Processor","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2007-03-02","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京工業大学大学院情報理工学研究科"},{"subitem_text_value":"東京工業大学工学部情報工学科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information Science and Engineering,Tokyo Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"School of Engineering, Tokyo Institute of Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/28852/files/IPSJ-HPC07109042.pdf"},"date":[{"dateType":"Available","dateValue":"2009-03-02"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-HPC07109042.pdf","filesize":[{"value":"554.0 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"14"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"80f40f6d-e352-483f-a667-295ea7ed4c61","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2007 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"吉瀬, 謙二"},{"creatorName":"佐々木, 豊"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Kenji, Kise","creatorNameLang":"en"},{"creatorName":"Yutaka, Sasaki","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10463942","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"今日のパイプライン段数の多い高性能プロセッサにおいては，分岐予測ミスのペナルティが大きいために分岐予測の精度がその性能を左右する．しかし最近では，回路面積の削減などのためにハードウェアでおこなう分岐予測を簡素化した高性能プロセッサが市場に出荷されている.そのような簡素なハードウェア分岐予測しか持たないプロセッサでは，分岐予測ミスが多発することで性能を低下するおそれがある．本稿では，簡素なハードウェア分岐予測しか持たないプロセッサを対象として，従来はハードウェアでおこなっていた分岐予測をソフトウェアで実現するソフトウェア分岐予測の枠組みを提案する．また，Cellプロセッサに含まれるSynergisticProcessorElementにおけるソフトウェア分岐予測の可能性を検討する．バブルソートをベースにして飽和型2ビットカウンタ方式のソフトウェア分岐予測を実装する場合に，予測精度の向上および分岐予測ミスペナルティの削減が可能であること，最大で17%の性能向上を得られることを確認する．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Accurate branch prediction is important for modern high performance processors. In order to improve the prediction accuracy, many hardware branch predictions have been investigated. On the other hand, a processor with very simple hardware branch prediction is appearing in a market. In this paper, we introduce the framework of software branch prediction that predicts branch outcome by software with minimal hardware support. We evaluate the framework on a Synergistic Processor Element of the Cell Broadband Engine Processor. Our preliminary experimental results using a bubble sort programs how that a software branch prediction of a two-bit saturating counter gives better prediction accuracy and achieves the maximum performance gain of 17%.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"250","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告ハイパフォーマンスコンピューティング（HPC）"}],"bibliographicPageStart":"245","bibliographicIssueDates":{"bibliographicIssueDate":"2007-03-02","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"17(2007-HPC-109)","bibliographicVolumeNumber":"2007"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"created":"2025-01-18T22:58:51.459299+00:00","id":28852,"links":{}}