{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00028371","sets":["1164:2036:2155:2156"]},"path":["2156"],"owner":"1","recid":"28371","title":["モジュールの再利用を考慮したフロアプラン設計手法の提案　?初期フロアプランニング?"],"pubdate":{"attribute_name":"公開日","attribute_value":"1987-12-17"},"_buckets":{"deposit":"6c63fa7e-1e67-4fff-9bec-7b781886f21b"},"_deposit":{"id":"28371","pid":{"type":"depid","value":"28371","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"モジュールの再利用を考慮したフロアプラン設計手法の提案　?初期フロアプランニング?","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"モジュールの再利用を考慮したフロアプラン設計手法の提案　?初期フロアプランニング?"},{"subitem_title":"A Floorplanning Method for Custom VLSI Chips Including Reused Modules -Initial Floorplanning Phase-","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1987-12-17","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"広島大学　工学部"},{"subitem_text_value":"広島大学　工学部"},{"subitem_text_value":"広島大学　工学部"},{"subitem_text_value":"大阪大学　基礎工学部"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Faculty of Engineering Hiroshima University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering Hiroshima University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering Hiroshima University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering Science Osaka University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering Science Osaka University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/28371/files/IPSJ-SLDM87040003.pdf"},"date":[{"dateType":"Available","dateValue":"1989-12-17"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM87040003.pdf","filesize":[{"value":"1.1 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"789142a7-91d0-4b43-9ef5-75ea664b42ab","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1987 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"大村道郎"},{"creatorName":"出本, 浩"},{"creatorName":"藤井, 隆志"},{"creatorName":"菊野, 亨"},{"creatorName":"吉田, 典司"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Michiroh, Ohmura","creatorNameLang":"en"},{"creatorName":"Hiroshi, Izumoto","creatorNameLang":"en"},{"creatorName":"Takashi, Fujii","creatorNameLang":"en"},{"creatorName":"Tohru, Kikuno","creatorNameLang":"en"},{"creatorName":"Noriyoshi, Yoshida","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"VLSIチップのレイアウト設計において，既に設計されているチップのモジュールを再利用することは，設計期間の短縮につながる．本稿では，筆者らにより提案されている階層化フロアプランニング手法における初期フロアプランニングの段階について，?モジュールを再利用することを前提とし，ハードモジュールの形状を凸XY多角形に拡張し，?チップ周辺の入出力パッドの位置を考慮した．本手法では，まず，モジュール間の結合度に応じて初期配置を行う．次に，各モジュールの位置を決定する．最後に，相対位置関係を保存しながら，チップの縦横比を満たし，且つ面積が最小になるよう重なりを除去する．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This paper discusses the initial phase of the floorplanning method proposed by the authors. First, convex rectilinear polygons are introduced in order to treat reused modules. Second, the positions of I/O pads are taken into consideration. In our method, a placement of modules is obtained based on the connectivity between modules. Then, orientations of modules are determined. Finally, overlaps of modules are resolved preserving relative positions, satisfying the aspect ratio, and minimizing the chip area.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"22","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"15","bibliographicIssueDates":{"bibliographicIssueDate":"1987-12-17","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"90(1987-SLDM-040)","bibliographicVolumeNumber":"1987"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":28371,"updated":"2025-01-22T18:05:22.182907+00:00","links":{},"created":"2025-01-18T22:58:29.876170+00:00"}