{"created":"2025-01-18T22:58:26.572537+00:00","updated":"2025-01-22T18:08:04.432657+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00028299","sets":["1164:2036:2143:2145"]},"path":["2145"],"owner":"1","recid":"28299","title":["テスト生成における並列処理の最適スケジューリング"],"pubdate":{"attribute_name":"公開日","attribute_value":"1989-10-24"},"_buckets":{"deposit":"758bfe6c-ef15-45c8-802c-f3297d2128ed"},"_deposit":{"id":"28299","pid":{"type":"depid","value":"28299","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"テスト生成における並列処理の最適スケジューリング","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"テスト生成における並列処理の最適スケジューリング"},{"subitem_title":"Optimal Schedule in Parallel Processing for Test Pattern Generation","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1989-10-24","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"明治大学理工学部"},{"subitem_text_value":"明治大学理工学部"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Department of Computer Science, Meiji University","subitem_text_language":"en"},{"subitem_text_value":"Department of Computer Science, Meiji University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/28299/files/IPSJ-SLDM89049013.pdf"},"date":[{"dateType":"Available","dateValue":"1991-10-24"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM89049013.pdf","filesize":[{"value":"897.7 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"3e557c33-e917-4c83-b8f3-15fb20031ef3","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1989 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"井上, 智生"},{"creatorName":"藤原, 秀雄"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Tomoo, Inoue","creatorNameLang":"en"},{"creatorName":"Hideo, Fujiwara","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"論理回路のテスト生成問題は，NP困難な問題として知られており，その処理にはバックトラック手法を用いるため，高速化は非常に困難である。本稿では，高速化の一方法として，汎用コンピュータの疎結合分散型ネットワークを用いたテスト生成並列処理を提案する。そして，各プロセッサへの部分問題の割り当ての効果，部分問題の粒度，シングル・プロセッサ・システムに対するマルチ・プロセッサ・システムのスピードアップ率を解析することにより，その性能を評価する。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"The problem of test generation for logic circuits is known to be NP-hard, and hence it is very hard to speed up the test generation process due to its backtracking mechanism. This paper presents and approach to parallel processing of test generation for logic circuits in a loosely-coupled distributed network of general purpose computers, and analyze the effects of the allocation of target faults to processors, the optimal granularity (grain size of larger faults) and the speedup ratio of the multiple-processor system to a single processor system.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"94","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"89","bibliographicIssueDates":{"bibliographicIssueDate":"1989-10-24","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"90(1989-SLDM-049)","bibliographicVolumeNumber":"1989"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":28299,"links":{}}