{"links":{},"id":28282,"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00028282","sets":["1164:2036:2143:2144"]},"path":["2144"],"owner":"1","recid":"28282","title":["論理合成システムLODESの論理最適化手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"1989-12-14"},"_buckets":{"deposit":"ca0930cc-7018-4a04-b9ac-f809f63e86eb"},"_deposit":{"id":"28282","pid":{"type":"depid","value":"28282","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"論理合成システムLODESの論理最適化手法","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"論理合成システムLODESの論理最適化手法"},{"subitem_title":"Logic Optimization For Logic Synthesis Expert System LODES","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1989-12-14","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"松下電子工業（株）開発推進センター"},{"subitem_text_value":"（株）松下ソフトリサーチ"},{"subitem_text_value":"（株）松下ソフトリサーチ"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Matsushita Electronics Co. Development Promotion Center","subitem_text_language":"en"},{"subitem_text_value":"Matsushita Soft Research Inc.","subitem_text_language":"en"},{"subitem_text_value":"Matsushita Soft Research Inc.","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/28282/files/IPSJ-SLDM89050012.pdf"},"date":[{"dateType":"Available","dateValue":"1991-12-14"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM89050012.pdf","filesize":[{"value":"565.9 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"4680acd8-6422-4723-935e-7072c50de1d6","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1989 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"横山, 敏之"},{"creatorName":"秋吉, 克一"},{"creatorName":"鈴木, 和代"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Toshiyuki, Yokoyama","creatorNameLang":"en"},{"creatorName":"Katsuichi, Akiyoshi","creatorNameLang":"en"},{"creatorName":"Kazuyo, Suzuki","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"LODESは機能記述言語、真理値表、論理式、機能図などの機能仕様を入力とし特定のテクノロジーの最適化された論理回路を出力する論理合成エキスパートシステムである。本システムの論理レベルの合成は、テクノロジーに依存しない組合せ論理の二段および多段の論理最適化をアルゴリズムによって、また局所変換を主体としたテクノロジーマッピングをルールベースの手法により構成している。本稿では、組合せ論理の最適化手法について述べる。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"LODES is a logic synthesis expert system, which accepts functional specifications such as hardware description language, boolean expressions, truth tables, functional diagrams and outputs optimized logic circuits of specified technology. In this system, logic level synthesis is realized as combination of algorithmic and rule-based methods, the former is two and multi level logic optimization independent of technology and the latter is technology mapping mainly based on local transformation. In this paper, we described about methods of combinatorial logic optimization for LODES.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"90","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"85","bibliographicIssueDates":{"bibliographicIssueDate":"1989-12-14","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"108(1989-SLDM-050)","bibliographicVolumeNumber":"1989"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"created":"2025-01-18T22:58:25.797298+00:00","updated":"2025-01-22T18:08:27.837395+00:00"}