{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00028279","sets":["1164:2036:2143:2144"]},"path":["2144"],"owner":"1","recid":"28279","title":["2段パスロジックによる非同期式順序回路の合成"],"pubdate":{"attribute_name":"公開日","attribute_value":"1989-12-14"},"_buckets":{"deposit":"afec58ee-6286-4f3d-b6d9-5e3852104483"},"_deposit":{"id":"28279","pid":{"type":"depid","value":"28279","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"2段パスロジックによる非同期式順序回路の合成","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"2段パスロジックによる非同期式順序回路の合成"},{"subitem_title":"Asynchronous sequential machine synthesis using Two - transistor pass logic","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1989-12-14","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京大学工学部"},{"subitem_text_value":"東京大学工学部"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"The faculty or Engineering, The university of tokyo","subitem_text_language":"en"},{"subitem_text_value":"The faculty or Engineering, The university of tokyo","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/28279/files/IPSJ-SLDM89050009.pdf"},"date":[{"dateType":"Available","dateValue":"1991-12-14"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM89050009.pdf","filesize":[{"value":"711.9 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"04575e13-9572-43f2-9d5a-70019b2c691c","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1989 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"趙慶録"},{"creatorName":"浅田, 邦博"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"K., R.Cho","creatorNameLang":"en"},{"creatorName":"K., Asada","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本稿では内部状態割当に線形コードを用いて2段パスロジック構造になる新しい非同期順序回路の合成手法を提案する。状態割当は遷移表の特性に依存せず一義的に行われ，レーシング・フリーは内部状態割当ではなく，状態変数を記憶する4FET'sセット・リセットフリップ・フロップとそれを駆動する回路で実現する。セットとリセットの駆動回路は各々のパス上に2つのトランジスタ（入カと状態変数）が置かれる2段パスロジック構造になっている。合成された回路は基本モード動作ではハザードフリーになるコンパクトな回路で，スタティックな電力消費がない。またハードウェアの大きさを他の手法と解析的に比較評価した。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This paper presents a new design method for asynchronous sequential machines, which utilizes two-transistor pass logic circuits and linear code state assignment. Memory elements for internal state codes are set-reset flip-flops. Each set-reset control circuit for flip-flops is synthesized as a two-transistor pass logic circuit, which has only two input variables on each pass. Synthesized circuits are hazard and critical race free, and compact, compared with other methods. It is shown that the present method gives the smallest circuit in terms of numbers of transistor for large transition tables (more 40cells).","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"70","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"63","bibliographicIssueDates":{"bibliographicIssueDate":"1989-12-14","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"108(1989-SLDM-050)","bibliographicVolumeNumber":"1989"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":28279,"updated":"2025-01-22T18:08:20.284316+00:00","links":{},"created":"2025-01-18T22:58:25.661214+00:00"}