{"id":28235,"updated":"2025-01-22T18:09:15.430828+00:00","links":{},"created":"2025-01-18T22:58:23.672600+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00028235","sets":["1164:2036:2137:2139"]},"path":["2139"],"owner":"1","recid":"28235","title":["命令実行によるプロセッサ制御回路の検査　－タイミングコントローラの検査を考慮したときのシーケンサ最小テスト集合の導出手続き－"],"pubdate":{"attribute_name":"公開日","attribute_value":"1990-10-08"},"_buckets":{"deposit":"7c276a5e-40a8-48f9-8165-411f287c16ea"},"_deposit":{"id":"28235","pid":{"type":"depid","value":"28235","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"命令実行によるプロセッサ制御回路の検査　－タイミングコントローラの検査を考慮したときのシーケンサ最小テスト集合の導出手続き－","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"命令実行によるプロセッサ制御回路の検査　－タイミングコントローラの検査を考慮したときのシーケンサ最小テスト集合の導出手続き－"},{"subitem_title":"Testing Processor Control Circuit with Instruction Execution -Minimum Test Set for Sequencer Considering Timing Controller Test-","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1990-10-08","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"岡山大学工学部"},{"subitem_text_value":"岡山大学工学部"},{"subitem_text_value":"岡山大学工学部"},{"subitem_text_value":"岡山大学工学部"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Faculty of Engineering Science, Okayama University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering Science, Okayama University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering Science, Okayama University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering Science, Okayama University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/28235/files/IPSJ-SLDM90054001.pdf"},"date":[{"dateType":"Available","dateValue":"1992-10-08"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM90054001.pdf","filesize":[{"value":"634.1 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"fca80bc6-7c33-4e25-9e9b-70eb9cc9d148","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1990 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"的場, 和男"},{"creatorName":"横平, 徳美"},{"creatorName":"杉山, 裕二"},{"creatorName":"岡本卓爾"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"K., Matoba","creatorNameLang":"en"},{"creatorName":"T., Yokohira","creatorNameLang":"en"},{"creatorName":"Y., Sugiyama","creatorNameLang":"en"},{"creatorName":"T., Okamotpo","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"プロセッサ制御回路は機能的にシーケンサ（），タイミングコントローラ（）およびコンディション・ディサイダに分割されるが，このうちのSCについては，命令実行により検査するという前提の下で，既に最小テスト集合(の入力と状態との組のすべてを生起する最小数の命令実行）導出法が与えられている．しかし，この方法では，並行して実施できるTCの検査が全く考慮されていない．本論文では，TCの検査も考慮したときのSCの最小テスト集合導出法を示している．この方法によれば，TCの入力と状態との組を最大限に検査できるような，SCの最小テスト集合が得られる．また，その最小テスト集合で生起できない(の）入力と状態との組に対するテスト集合の要素数は最小となる．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"A processor contlor circuit can be separated into three blocks, Sequencer (SC), Timing Controller (TC), Condition Decider. There are some studies on testing each block with instruction executions, where a test set is a set of instruction executions which generate all of the input-state vectors in the block. This paper describes a method of generating the minimum test set for SC which covers the input-state vectors in TC as many as possible. In case of Intel 8080 processors, about 95 percent of the input-state vectors in TC are covered by the test set for SC obtained by the use of the method.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"8","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"1990-10-08","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"81(1990-SLDM-054)","bibliographicVolumeNumber":"1990"}]},"relation_version_is_last":true,"weko_creator_id":"1"}}