{"created":"2025-01-18T22:58:23.353989+00:00","updated":"2025-01-22T18:09:53.168909+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00028228","sets":["1164:2036:2137:2138"]},"path":["2138"],"owner":"1","recid":"28228","title":["許容関数集合に基づく組合せ論理回路の遅延最適化"],"pubdate":{"attribute_name":"公開日","attribute_value":"1990-12-12"},"_buckets":{"deposit":"d4e411eb-ed82-4e57-bdda-cb4bcb7f034e"},"_deposit":{"id":"28228","pid":{"type":"depid","value":"28228","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"許容関数集合に基づく組合せ論理回路の遅延最適化","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"許容関数集合に基づく組合せ論理回路の遅延最適化"},{"subitem_title":"Delay Time Optimization for Combinational Circuits based on the Permissible Functions","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1990-12-12","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"シャープ株式会社"},{"subitem_text_value":"シャープ株式会社"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"SHARP Corporation","subitem_text_language":"en"},{"subitem_text_value":"SHARP Corporation","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/28228/files/IPSJ-SLDM90055010.pdf"},"date":[{"dateType":"Available","dateValue":"1992-12-12"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM90055010.pdf","filesize":[{"value":"495.5 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"8bb3da28-534b-4f7e-af42-567dd955bdf1","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1990 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"藤本, 徹哉"},{"creatorName":"神戸尚志"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"T., Fujimoto","creatorNameLang":"en"},{"creatorName":"T., Kambe","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"近年、論理合成技術の実用化にともない、遅延時間に関する仕様を満足した回路を合成できる論理合成システムが要請されている。本論文では、遅延時間を大域的に最適化することを目的として、許容関数集合の概念に基づいて論理回路の段数を最小化する二つのプール的手法を提案する。これは、面積コストの最適化に関して強力なアルゴリスムとされてきたトランスダクション法の一拡張である。本手法を用いて論理回路を大域的に変換することにより、論理回路の段数を大きく削減できること、および面積最適化とテクノロジマッピングを適用した後の遅延時間も、さらに改善されることが実験により示された。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Logic synthesis technology is nowadays getting practical in designing commercial chips, consequently logic synthesis system is required to be capable for satisfying specifications in terms of circuit delay. In this paper, in order of global timing optimization, we present two boolean algorithms for logic-depth minimization based on the concept of the Set of Permissible Functions. Our approarch is an extention from the Transduction Method which is a fairly effective algorithm for area minimization, By the use of the presented method, it is shown that logic depth of given circuits is reduced effectively and also circuit delay even after area minimization and technology mapping.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"78","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"73","bibliographicIssueDates":{"bibliographicIssueDate":"1990-12-12","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"100(1990-SLDM-055)","bibliographicVolumeNumber":"1990"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":28228,"links":{}}