{"updated":"2025-01-22T18:13:01.439918+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00028147","sets":["1164:2036:2126:2129"]},"path":["2129"],"owner":"1","recid":"28147","title":["FPGAを対象としたトップダウン配線手法の実装と評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"1992-05-27"},"_buckets":{"deposit":"30d19db2-53ea-44b3-8c37-4f8ce69a8ac8"},"_deposit":{"id":"28147","pid":{"type":"depid","value":"28147","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"FPGAを対象としたトップダウン配線手法の実装と評価","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"FPGAを対象としたトップダウン配線手法の実装と評価"},{"subitem_title":"Implementation and Estimation of a Top - down Routing Algorithm for Field Programmable Gate Array","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1992-05-27","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"早稲田大学　理工学部"},{"subitem_text_value":"早稲田大学　理工学部"},{"subitem_text_value":"早稲田大学　理工学部"},{"subitem_text_value":"早稲田大学　理工学部"},{"subitem_text_value":"早稲田大学　理工学部"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"School of Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"School of Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"School of Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"School of Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"School of Science and Engineering, Waseda University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/28147/files/IPSJ-SLDM92062038.pdf"},"date":[{"dateType":"Available","dateValue":"1994-05-27"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM92062038.pdf","filesize":[{"value":"824.3 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"cb90e30d-28dc-432b-9f25-8f8a1b44ef0e","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1992 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"粟島, 亨"},{"creatorName":"戸川, 望"},{"creatorName":"金子, 一哉"},{"creatorName":"佐藤政生"},{"creatorName":"大附, 辰夫"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Toru, Awashima","creatorNameLang":"en"},{"creatorName":"Nozomu, Togawa","creatorNameLang":"en"},{"creatorName":"Kazuya, Kaneko","creatorNameLang":"en"},{"creatorName":"Masao, Sato","creatorNameLang":"en"},{"creatorName":"Tatsuo, Ohtsuki","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"FPGAを対象としたトップダウン配線手法を提案する．本手法は，sea?of?gates等を対象とした概略配線手法を拡張したもので，チップ領域を再帰的に2分割し，その分割線上のネットの通過位置を線形割当てによって決定するというトップダウン処理に基づいている．さらに，本手法では，2段階の線形割当てにより分割線と交差するネットの通過トラックをも決定してしまうことで，概略配線と詳細配線の一括処理を可能とし，高速な処理を実現している．従来用いられてきたCGEアルゴリズムと比較実験を行った結果，配線達成率に関しては両者がほぼ同等の性能であったが，処理時間に関しては本手法が40%?60%高速であることが確認できた．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"A top-down routing algorithm for field programmable gate array (FPGA) is proposed. The algorithm is extension of a top-down global routing algorithm which is based on a fast top-down bi-partitioning process of a routing region. During each partitioning, the algorithm determines not only global position but detailed position, say track position, of each net crossing a cut-line using a two-phase linear-assignment algorithm. Thus a detailed routing phase is no longer necessary. Experimental results show that the algorithm is approximately two times faster than CGE algorithm which is based on a traditional two-phase approach, while routing results are comparable.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"228","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"223","bibliographicIssueDates":{"bibliographicIssueDate":"1992-05-27","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"43(1992-SLDM-062)","bibliographicVolumeNumber":"1992"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"created":"2025-01-18T22:58:19.715537+00:00","id":28147,"links":{}}