{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00028092","sets":["1164:2036:2126:2127"]},"path":["2127"],"owner":"1","recid":"28092","title":["MullerのC素子を用いた非同期式順序回路の一構成法"],"pubdate":{"attribute_name":"公開日","attribute_value":"1992-10-22"},"_buckets":{"deposit":"498a57f2-0038-4059-95d2-9f4d7542a41a"},"_deposit":{"id":"28092","pid":{"type":"depid","value":"28092","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"MullerのC素子を用いた非同期式順序回路の一構成法","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"MullerのC素子を用いた非同期式順序回路の一構成法"},{"subitem_title":"Asynchronous Sequential Circuit Synthesis using Muller's C - elements","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1992-10-22","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京工業大学　工学部"},{"subitem_text_value":"東京工業大学　工学部"},{"subitem_text_value":"東京工業大学　工学部"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Faculty of Engineering, Tokyo Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering, Tokyo Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering, Tokyo Institute of Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/28092/files/IPSJ-SLDM92064004.pdf"},"date":[{"dateType":"Available","dateValue":"1994-10-22"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM92064004.pdf","filesize":[{"value":"965.3 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"8083aa65-a54b-47d2-8901-781ebfbc4872","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1992 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"黄亜紅"},{"creatorName":"籠谷, 裕人"},{"creatorName":"南谷, 崇"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Ya-Hong, Huang","creatorNameLang":"en"},{"creatorName":"Hiroto, Kagotani","creatorNameLang":"en"},{"creatorName":"Takashi, Nanya","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"MullerのC素子と呼ばれる2状態記憶素子は非同期式回路のタイミング制御用にしばしば用いられるが、C素子を用いた組織的な回路構成法に関する研究はこれまでほとんどない。一方、セットリセット型フリップフロップを記憶素子とする非同期式順序回路の構成法は良く知られている。C素子の状態遷移特性はセットリセット型フリップフロップのそれを含むので、C素子を記憶素子として用いる非同期式順序回路の状態変数回路（記憶素子を駆動する論理回路）はセットリセット型フリップフロップを用いた場合よりも一般には常に簡単になる。本稿ではC素子を記憶素子として用いる非同期式順序回路の一構成法を示す。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Muller's C-element is a 2 state memory device, that is often used for timing control in asynchronous systems. However there has been nearly no research about logic synthesis using the C-element. On the other hand asynchronous sequential circuit synthesis using the set-reset flipflop is well known. As the state transition set of the C-element is a superset of the set-reset flipflop then we can use the C-element to synthesize asynchronous sequential circuits that, in general, will be simple then those using the set-reset flipflop. This paper describes a method for synthesing asynchronous sequential circuits using the C-element.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"32","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"25","bibliographicIssueDates":{"bibliographicIssueDate":"1992-10-22","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"83(1992-SLDM-064)","bibliographicVolumeNumber":"1992"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":28092,"updated":"2025-01-22T18:13:24.281326+00:00","links":{},"created":"2025-01-18T22:58:17.257701+00:00"}