{"created":"2025-01-18T22:58:15.490804+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00028056","sets":["1164:2036:2120:2123"]},"path":["2123"],"owner":"1","recid":"28056","title":["三段NANDゲート回路の一設計法"],"pubdate":{"attribute_name":"公開日","attribute_value":"1993-06-25"},"_buckets":{"deposit":"e7b3eb9a-06d4-45dd-8736-340f8a2d0a1b"},"_deposit":{"id":"28056","pid":{"type":"depid","value":"28056","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"三段NANDゲート回路の一設計法","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"三段NANDゲート回路の一設計法"},{"subitem_title":"An Algorithm for Finding a Minimal Three - Level NAND Network","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1993-06-25","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"富山大学　工学部"},{"subitem_text_value":"富山大学　工学部"},{"subitem_text_value":"富山大学　工学部"},{"subitem_text_value":"富山大学　工学部"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Faculty of Engineering, Toyama University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering, Toyama University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering, Toyama University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering, Toyama University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/28056/files/IPSJ-SLDM93067007.pdf"},"date":[{"dateType":"Available","dateValue":"1995-06-25"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM93067007.pdf","filesize":[{"value":"1.1 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"57e5e0d1-f426-4465-a4a9-94f54c09f7ba","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1993 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"宮腰, 隆"},{"creatorName":"大澤, 一人"},{"creatorName":"松田, 秀雄"},{"creatorName":"畠山, 豊正"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Takashi, Miyagoshi","creatorNameLang":"en"},{"creatorName":"Kazuto, Oosawa","creatorNameLang":"en"},{"creatorName":"Hideo, Matsuda","creatorNameLang":"en"},{"creatorName":"Toyomasa, Hatakeyama","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"三段NANDゲート回路の（ゲート数，入力線数）最小化設計の一手法が提案される．初めに，P許容項からN許容項を打ち抜くという考えに基づくP?N項法が述べられる．ついで，多段NANDゲート回路を三段NAND回路に直し，これを初期回路として，二段ゲートの個数を減らすために，P許容項の拡大，三段ゲートの個数を減らすために最小被覆表を使って，回路を簡単化するMA3法が述べられる．MA3法は原理的にP?N項法と同じであるが，多変数の関数に適用される．MA3法は4変数関数で後藤の方法と比較しゲート数でほぼ同等の回路が得られることが示される．また，9変数までの関数なら全部，10変数の関数については真理値表濃度が0．55までなら計算できることが示される．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"A method for the logical design of minimal three-level NAND gate network is proposed. First the P-N term method which is based on the idea cutting out N (egative permissible) terms from a P (ositive termissible) term is explained. Then the MA3 method being improved to apply to more variable functions is described. In the method, a multi-level NAND network is transformed to a three-level NAND network. P-terms are expanded to reduce the number of the second level gate. and a minimum cover table is used to reduce the number of input gates. The MA3 method is able to find the network for the whole of the function up to 9 variables and 10 variable functions which the truth-table-density are less than 0.55.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"54","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"47","bibliographicIssueDates":{"bibliographicIssueDate":"1993-06-25","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"55(1993-SLDM-067)","bibliographicVolumeNumber":"1993"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":28056,"updated":"2025-01-22T18:14:26.484384+00:00","links":{}}