@techreport{oai:ipsj.ixsq.nii.ac.jp:00028056,
 author = {宮腰, 隆 and 大澤, 一人 and 松田, 秀雄 and 畠山, 豊正 and Takashi, Miyagoshi and Kazuto, Oosawa and Hideo, Matsuda and Toyomasa, Hatakeyama},
 issue = {55(1993-SLDM-067)},
 month = {Jun},
 note = {三段NANDゲート回路の（ゲート数，入力線数）最小化設計の一手法が提案される．初めに，P許容項からN許容項を打ち抜くという考えに基づくP?N項法が述べられる．ついで，多段NANDゲート回路を三段NAND回路に直し，これを初期回路として，二段ゲートの個数を減らすために，P許容項の拡大，三段ゲートの個数を減らすために最小被覆表を使って，回路を簡単化するMA3法が述べられる．MA3法は原理的にP?N項法と同じであるが，多変数の関数に適用される．MA3法は4変数関数で後藤の方法と比較しゲート数でほぼ同等の回路が得られることが示される．また，9変数までの関数なら全部，10変数の関数については真理値表濃度が0．55までなら計算できることが示される．, A method for the logical design of minimal three-level NAND gate network is proposed. First the P-N term method which is based on the idea cutting out N (egative permissible) terms from a P (ositive termissible) term is explained. Then the MA3 method being improved to apply to more variable functions is described. In the method, a multi-level NAND network is transformed to a three-level NAND network. P-terms are expanded to reduce the number of the second level gate. and a minimum cover table is used to reduce the number of input gates. The MA3 method is able to find the network for the whole of the function up to 9 variables and 10 variable functions which the truth-table-density are less than 0.55.},
 title = {三段NANDゲート回路の一設計法},
 year = {1993}
}