{"created":"2025-01-18T22:58:15.134306+00:00","updated":"2025-01-22T18:15:07.401424+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00028048","sets":["1164:2036:2120:2122"]},"path":["2122"],"owner":"1","recid":"28048","title":["2相式非同期回路高速化のための基本制御モジュールとその応用"],"pubdate":{"attribute_name":"公開日","attribute_value":"1993-10-28"},"_buckets":{"deposit":"d9d6c5c4-9f9e-42ed-a974-8126611e429e"},"_deposit":{"id":"28048","pid":{"type":"depid","value":"28048","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"2相式非同期回路高速化のための基本制御モジュールとその応用","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"2相式非同期回路高速化のための基本制御モジュールとその応用"},{"subitem_title":"On Handshake Control for 2 - phase Delay - insensitive Processors","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1993-10-28","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京工業大学　工学部"},{"subitem_text_value":"東京工業大学　工学部"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Faculty of Engineering, Tokyo Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering, Tokyo Institute of Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/28048/files/IPSJ-SLDM93068022.pdf"},"date":[{"dateType":"Available","dateValue":"1995-10-28"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM93068022.pdf","filesize":[{"value":"1.0 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"074b57b5-53aa-4c0d-b2f5-8f9635207c5c","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1993 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"籠谷, 裕人"},{"creatorName":"南谷, 崇"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Hiroto, Kagotani","creatorNameLang":"en"},{"creatorName":"Takashi, Nanya","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"非同期式回路のデータパスを稼働相と休止相の2相で動作させる場合に、次の動作に進む前に本来の機能ではない休止相の完了を待つことは無駄である。本稿では休止相を待たずに次に進むことを許す基本制御モジュールを提案し、従来の制御モジュールをこれに置換することによる高速化を議論する。単純な置換ができない箇所は、依存性グラフの解析により明らかになる。このような箇所においても、付加的な回路を使用することで、ゲートの遅延に依存せずに休止相のほとんどを隠蔽することが可能になる。論理シミュレーションにより、本手法でゲート数の増大なしに大幅な速度向上が可能なことが実証された。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In 2-phase delay-insensitive circuits, approximately a half of the processing time is wasted by the second phase called idle phase that does not perform any actual operation. We propose a handshake controller that entables next operations to start without waiting for the completion of the idle phase so that we can reduce the processing time. Replacing a conventional control module simply with the new module is not always allowed because of the dependencies. We solved this problem by using additional AND gates. Logic simulation shows that this method can improve the throughput of circuits without increasing the number of the gates.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"170","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"163","bibliographicIssueDates":{"bibliographicIssueDate":"1993-10-28","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"94(1993-SLDM-068)","bibliographicVolumeNumber":"1993"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":28048,"links":{}}