{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00028005","sets":["1164:2036:2120:2121"]},"path":["2121"],"owner":"1","recid":"28005","title":["シミュレーティド・アニーリングを用いたテクノロジーマッピング"],"pubdate":{"attribute_name":"公開日","attribute_value":"1993-12-16"},"_buckets":{"deposit":"e1c56058-1321-4905-ac26-b57a2ea94fdc"},"_deposit":{"id":"28005","pid":{"type":"depid","value":"28005","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"シミュレーティド・アニーリングを用いたテクノロジーマッピング","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"シミュレーティド・アニーリングを用いたテクノロジーマッピング"},{"subitem_title":"Technology Mapping with Simulated Annealing","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1993-12-16","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"大阪府立大学工学部"},{"subitem_text_value":"大阪府立大学工学部"},{"subitem_text_value":"大阪府立大学工学部"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Fuculty of Engineering, University of OSAKA Prefecture","subitem_text_language":"en"},{"subitem_text_value":"Fuculty of Engineering, University of OSAKA Prefecture","subitem_text_language":"en"},{"subitem_text_value":"Fuculty of Engineering, University of OSAKA Prefecture","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/28005/files/IPSJ-SLDM93069003.pdf"},"date":[{"dateType":"Available","dateValue":"1995-12-16"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM93069003.pdf","filesize":[{"value":"664.7 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"3427be26-9fc0-4393-b127-1ef737ebafb5","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1993 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"原嶋, 勝美"},{"creatorName":"福永, 邦雄"},{"creatorName":"小迫, 秀夫"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Katsumi, Harashima","creatorNameLang":"en"},{"creatorName":"Kunio, Fukunaga","creatorNameLang":"en"},{"creatorName":"Hideo, Kosako","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本稿では、高速化を目標としたテクノロジーマッピングについて述べる。従来レイアウト設計における配置手法として利用されていたシミュレーティドアニーリング法は、逐次改善処理において局所最適解に陥りることを避けようとする方法であるが、多くの処理時間が必要である。そこで、温度パラメータを解の改善度に基づいて非線形に減少させることにより高速化を図り、テクノロジーマッピングに用いた。その結果、既存のテクノロジーマッピング・システムに比べ、処理時間は3倍?19倍になり、得られた回路の遅延時間および面積ともに、同程度以上の結果が得られた。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In this paper, we will present a technology mapping with the improved simulated annealing. Simulated annealing methods have been used for placement circuit modules in the layout phase, can get good solutions. However, they are very slowly. Therefor, we attempt this method speed-up decreasing a temperature-parameter non-linealy, and apply this one to a technology-mapping. As a result of, our method is faster than the logic synthesis system MIS and gets good solutions.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"22","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"17","bibliographicIssueDates":{"bibliographicIssueDate":"1993-12-16","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"111(1993-SLDM-069)","bibliographicVolumeNumber":"1993"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":28005,"updated":"2025-01-22T18:15:12.894748+00:00","links":{},"created":"2025-01-18T22:58:13.229042+00:00"}