{"created":"2025-01-18T22:58:10.159777+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00027936","sets":["1164:2036:2109:2114"]},"path":["2114"],"owner":"1","recid":"27936","title":["ビアの削減を目的とした階層的概略配線手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"1995-03-08"},"_buckets":{"deposit":"5dbb5034-cf0d-4a39-822b-2de6fc9ec907"},"_deposit":{"id":"27936","pid":{"type":"depid","value":"27936","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"ビアの削減を目的とした階層的概略配線手法","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"ビアの削減を目的とした階層的概略配線手法"},{"subitem_title":"A Hierarchical Global Routing Algorithm with Via Reduction","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1995-03-08","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"早稲田大学理工学部"},{"subitem_text_value":"早稲田大学理工学部"},{"subitem_text_value":"早稲田大学理工学部"},{"subitem_text_value":"早稲田大学理工学部"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"School of Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"School of Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"School of Science and Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"School of Science and Engineering, Waseda University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/27936/files/IPSJ-SLDM94074006.pdf"},"date":[{"dateType":"Available","dateValue":"1997-03-08"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM94074006.pdf","filesize":[{"value":"1.3 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"20907c86-9911-4d03-9818-9bec4de59ea4","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1995 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"金沢, 正博"},{"creatorName":"田中, 秀彦"},{"creatorName":"佐藤政生"},{"creatorName":"大附, 辰夫"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Masahiro, Kanazawa","creatorNameLang":"en"},{"creatorName":"Hidehiko, Tanaka","creatorNameLang":"en"},{"creatorName":"Masao, Sato","creatorNameLang":"en"},{"creatorName":"Tatsuo, Ohtsuki","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"ゲートアレイやビルディングブロック・レイアウトに対する概略配線手法として，線形割当てに基づく階層的概略配線手法が提案されている．この手法は配線領域全体を概略格子によって分割した矩形領域を処理単位としたもので，再帰的に領域を分割し，適当なコストに基づいて最終的に各ネットの通過する領域を決定する．しかし，この手法では，概略径路のパタンが複雑化することにより，この段階でのビアの数が多くなってしまう．そこで，端子位置主導型のコスト関数を導入することでビア削減を目指した概略配線手法を提案し，計算機実験によってその効果を確認する．また，この手法を，平面配線が得意で柔軟なトポロジカルなレイアウト表現を用いたスケッチレイアウトシステムのための概略配線手法に応用するため，層割当て手法と端子位置の決定手法について提案する．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Several hierarchical global routing algorithms based on linear assignments have been proposed and widespread. They bi-partition a given routing region recursively and assign a global position for net crossing a cut-line by using linear assignments according to defined costs. A drawback of the algotithms is to generate zigzag routing patterns, which could lead a lot of vias. A new hierarchical global routing algorithm which generates less vias by improving cost functions is presented in this paper. Experimental results show its efficiency. Algorithms for layer assignment and determining terminal positions are also presented. Those algorithms are necessary to apply the presented global router to sketch layout systems.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"48","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"41","bibliographicIssueDates":{"bibliographicIssueDate":"1995-03-08","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"24(1994-SLDM-074)","bibliographicVolumeNumber":"1995"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":27936,"updated":"2025-01-22T18:17:35.791230+00:00","links":{}}