{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00027837","sets":["1164:2036:2104:2106"]},"path":["2106"],"owner":"1","recid":"27837","title":["識別可能な多値レベルを考慮したニューロンMOS論理素子設計手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"1996-10-17"},"_buckets":{"deposit":"eef00c02-5aa4-4963-b54d-3a7c88ee94c4"},"_deposit":{"id":"27837","pid":{"type":"depid","value":"27837","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"識別可能な多値レベルを考慮したニューロンMOS論理素子設計手法","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"識別可能な多値レベルを考慮したニューロンMOS論理素子設計手法"},{"subitem_title":"A Design Method of Logic Elements Using Neuron MOS Transistors Considering the Number of Multiple - Valued Logic Levels","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1996-10-17","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"九州大学大学院システム情報科学研究科情報工学専攻"},{"subitem_text_value":"九州大学大学院システム情報科学研究科情報工学専攻"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Department of Computer Science and Communication Engineering Graduate School of Information Science and Electrical Engineering Kyushu University","subitem_text_language":"en"},{"subitem_text_value":"Department of Computer Science and Communication Engineering Graduate School of Information Science and Electrical Engineering Kyushu University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/27837/files/IPSJ-SLDM96081005.pdf"},"date":[{"dateType":"Available","dateValue":"1998-10-17"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM96081005.pdf","filesize":[{"value":"537.8 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"4cc4ea8e-5661-48ae-8aa9-b5380dd09742","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1996 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"池, 兼次郎"},{"creatorName":"安浦, 寛人"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Kenjirou, Ike","creatorNameLang":"en"},{"creatorName":"Hiroto, Yasuura","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"ニューロンMOSトランジスタ(euMO)は複数の入力ゲートを持ち，全入力信号の重みつき加算を行った結果に対してしきい動作をする高機能デバイスである．本稿ではまずneuMOSがデバイス内部で多値論理を扱い，内部で識別可能な多値レベル数がneuMOS回路を設計する上で大きな設計制約になることを述べる．次にこれまで検討を行ってきた2段neuMOS回路の特徴と問題点を指摘し，回路構成により自由度を持たせた多段neuMOS回路の構成を述べ，その設計手法を提案する．最後に本手法を用いたすべての3変数論理関数に対する設計結果を示す．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"A neuron MOS transistor, abbreviated to a neuMOS, has more than two input gates. It is highly functional device which realizes a switching operations as a threshold function of the weighted sum of all binary in put signals. NeuMOS deals with multiple-valued logic in the device and the number of recognizable logic levels in neuMOS is a major constraint on designing neuMOS circuits. We point out feature and problems of a 2-level neuMOS circuit, which we have studied. We propose a design method of a multi-level neuMOS circuit which has more degree of freedom on a circuit structure than the 2-level neuMOS circuit. Using this method, we generate multi-level neuMOS circuits for all 3-variable logic functions.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"40","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"33","bibliographicIssueDates":{"bibliographicIssueDate":"1996-10-17","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"101(1996-SLDM-081)","bibliographicVolumeNumber":"1996"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":27837,"updated":"2025-01-22T18:20:17.868417+00:00","links":{},"created":"2025-01-18T22:58:05.757934+00:00"}