{"created":"2025-01-18T22:58:00.558817+00:00","updated":"2025-01-22T18:24:03.561280+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00027719","sets":["1164:2036:2094:2095"]},"path":["2095"],"owner":"1","recid":"27719","title":["FPGAのマクロブロックを対象とした配置概略配線同時処理手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"1998-12-10"},"_buckets":{"deposit":"36fdbd91-eaef-4bab-a1c0-ad20688b441d"},"_deposit":{"id":"27719","pid":{"type":"depid","value":"27719","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"FPGAのマクロブロックを対象とした配置概略配線同時処理手法","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"FPGAのマクロブロックを対象とした配置概略配線同時処理手法"},{"subitem_title":"A Simultaneous Placement and Global Routing Algorithm for FPGAs with Macro - Blocks","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1998-12-10","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"早稲田大学理工学部電子・情報通信学科"},{"subitem_text_value":"早稲田大学理工学部電子・情報通信学科"},{"subitem_text_value":"早稲田大学理工学部電子・情報通信学科"},{"subitem_text_value":"早稲田大学理工学部電子・情報通信学科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Dept. of Electronics, Information and Communication Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Dept. of Electronics, Information and Communication Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Dept. of Electronics, Information and Communication Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Dept. of Electronics, Information and Communication Engineering, Waseda University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/27719/files/IPSJ-SLDM98090017.pdf"},"date":[{"dateType":"Available","dateValue":"2000-12-10"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM98090017.pdf","filesize":[{"value":"842.2 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"1634aa7b-91b7-4d61-a18f-32897b39df88","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1998 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"井上, 大輔"},{"creatorName":"戸川, 望"},{"creatorName":"柳澤, 政生"},{"creatorName":"大附, 辰夫"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Daisuke, Inoue","creatorNameLang":"en"},{"creatorName":"Nozomu, Togawa","creatorNameLang":"en"},{"creatorName":"Masao, Yanagisawa","creatorNameLang":"en"},{"creatorName":"Tatsuo, Ohtsuki","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"FPGAのマクロブロックとは，FPGA上で複数の論理ブロックがまとまって1つの機能を実現するブロック集合である．マクロブロックはFPGAの周波数を上げるためやFPGAの論理ブロックの使用率を上げるのに不可欠である．このマクロブロックのレイアウトでは，単純な論理ブロックの交換やレイアウト領域の分割による配置配線は適用できない．本稿では，このようなFPGAのマクロブロックを対象として，トップダウン分割とボトムアップ結合を組み合わせた配置概略配線同時処理手法を提案する．提案手法は，トップダウン分割段階とボトムアップ配置概略配線段階の2段階で構成される．トップダウン分割段階ではマクロブロック間の配線を考慮しながら階層的にレイアウト領域を分割する．ボトムアップ配置概略配線段階では 階層的にマクロブロックを配置概略配線しながら結合する．計算機実験により手法の有効性を評価した結果を報告する．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"A macro-block of FPGAs is a set of preplaced and prerouted logic-blocks wihich can imprement a logic function such as an adder or a multiplier. Macro-blocks are indispensable to increase the clock frequency and also logic-block utilization of an FPGA chip. This paper proposes a simultaneous placement and grobal routing algorithm for FPGAs with macro-blocks. The algorithm consists of top-down partitioning and bottom-up combining. The top-down partitioning phase is based on hierarchical bipartitioning of a layout region and a set of macro-block. If there exist connections between bipartitioned macroblock sets, pseudo-pins are introduced to perserve the connections. In this phase rough information for macro-block placement and global routing can be obtained. The Bottom-up combining phase combines partitioned layout regions and macro-blocks and determines datailed placement. The experimental results demonstrate the efficiency and effectiveness of the algorithm.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"130","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"123","bibliographicIssueDates":{"bibliographicIssueDate":"1998-12-10","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"113(1998-SLDM-090)","bibliographicVolumeNumber":"1998"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":27719,"links":{}}