{"id":27683,"updated":"2025-01-22T18:25:02.043793+00:00","links":{},"created":"2025-01-18T22:57:58.963194+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00027683","sets":["1164:2036:2090:2092"]},"path":["2092"],"owner":"1","recid":"27683","title":["FPGAs用論理合成のための関数分解手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"1999-09-20"},"_buckets":{"deposit":"2a38b062-024d-4d75-acc0-6dfbd150185b"},"_deposit":{"id":"27683","pid":{"type":"depid","value":"27683","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"FPGAs用論理合成のための関数分解手法","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"FPGAs用論理合成のための関数分解手法"},{"subitem_title":"Finding a good functional decomposition and its application to logic synthesis for LUT - based FPGAs","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1999-09-20","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京大学工学系研究科電子工学専攻"},{"subitem_text_value":"東京大学工学系研究科電子工学専攻"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Dept. of Electronic Eng., Univ. of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"Dept. of Electronic Eng., Univ. of Tokyo","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/27683/files/IPSJ-SLDM99092001.pdf"},"date":[{"dateType":"Available","dateValue":"2001-09-20"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM99092001.pdf","filesize":[{"value":"600.0 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"103fcc52-09ce-4247-8877-9fab61aa2018","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1999 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"喬健"},{"creatorName":"浅田, 邦博"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Jian, Qiao","creatorNameLang":"en"},{"creatorName":"Kunihiro, Asada","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本稿では、ルックアップテーブル(LookUp?Table)ベースのFPGAsの論理合成用関数分解の手法を紹介する。特に、面積最小（LUT数とかCLB数とかの最小）のための、関数分解にあたってのバウンド集合変数の抽出手法、及び部分依存の関数分解(Partially-dependent decomposition)、非離接性の関数分解(Non- disjunctive decomposition)のためののコンパットブルクラス(Compatible Class)のエンコーディング手法を提案する。ベンチマーク回路に対する初期の実験結果も報告し、大部の用例ではLUT数の減少が見られ、提案手法が有効であることが明らかになった。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This paper presents a logic synthesis approach for LUT-based FPGAs. Targeting area-minimization, our approach is based on functional decomposition. In the stage of bound-set variable's selection, we employ enumerative techniques in trying to find all simple decomposition or to find a good decomposition which has less compatible classes. In the stage of α function encoding, we try to get all possible non-disjuctive decoposition or partially-dependent decomposition to minimize the number of LUTs/CLBs. The preliminary experimental results from a set of MCNC and ISCS benchmarks show that the approach is quite promising.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"7","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"1999-09-20","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"75(1999-SLDM-092)","bibliographicVolumeNumber":"1999"}]},"relation_version_is_last":true,"weko_creator_id":"1"}}