{"links":{},"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00027654","sets":["1164:2036:2084:2089"]},"path":["2089"],"owner":"10","recid":"27654","title":["ビットシリアルFPGAシステムの開発"],"pubdate":{"attribute_name":"公開日","attribute_value":"2000-01-12"},"_buckets":{"deposit":"5fbdd2d1-a82d-4486-bc34-e55e185cee9c"},"_deposit":{"id":"27654","pid":{"type":"depid","value":"27654","revision_id":0},"owners":[10],"status":"published","created_by":10},"item_title":"ビットシリアルFPGAシステムの開発","author_link":["466456","466457","466459","466454","466455","466458"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"ビットシリアルFPGAシステムの開発"},{"subitem_title":"Development of Bit - Serial FPGA System","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2000-01-12","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京工業大学電気・電子工学科"},{"subitem_text_value":"東京工業大学電気・電子工学科"},{"subitem_text_value":"東京工業大学電気・電子工学科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Dept. of Electrical and Electronic Engineering","subitem_text_language":"en"},{"subitem_text_value":"Dept. of Electrical and Electronic Engineering","subitem_text_language":"en"},{"subitem_text_value":"Dept. of Electrical and Electronic Engineering","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/27654/files/IPSJ-SLDM99094010.pdf","label":"IPSJ-SLDM99094010"},"date":[{"dateType":"Available","dateValue":"2002-01-12"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM99094010.pdf","filesize":[{"value":"1.2 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"2d088e9a-b222-4d05-bf35-a6aed72ce2d0","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2000 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"一色, 剛"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"太田, 章久"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"國枝, 博昭"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Tsuyoshi, Isshiki","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Akihisa, Ohta","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hiroaki, Kunieda","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"FPGAの設計において，設計自動化ツールは必須であるが，これらのツールが生成する回路は多くの場合，配線性に乏しいため論理使用効率の低下や回路速度の低下を招いているのが現状である．我々は，この設計自動化と論理使用効率・パフォーマンスの向上の両立という目的のもと，ビットシリアル回路に基づいたFPGA上での設計について研究を進めている．本論文では，我々が現在まで行って来たビットシリアル回路設計，アプリケーション設計環境の構築，新たなビットシリアル用FPGAアーキテクチャの開発，等についてまとめ，さらに今現在進行している研究について述べる．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Design automation is essential in FPGA designs. However, the circuits generated by these synthesis tools tends to have poor circuit routability, resulting in low logic utilization and/or low circuit speed. We have been investigating the use of bit-serial circuits in FPGA environment to address this difficult issues of incorporating design automation while guaranteeing a highly efficient routability of the circuit, therefore increasing the silicon utilization and improving performance. Our research stems widely from bit-serial circuit designs, development of application design environment, development of new FPGA architectures, as well as new FPGA applications. In this paper, we summarize our work on these issues as well as some of the current on-going researches.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"80","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"73","bibliographicIssueDates":{"bibliographicIssueDate":"2000-01-12","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"2(1999-SLDM-094)","bibliographicVolumeNumber":"2000"}]},"relation_version_is_last":true,"weko_creator_id":"10"},"updated":"2025-01-19T22:59:50.366735+00:00","created":"2025-01-18T22:57:57.629125+00:00","id":27654}