@techreport{oai:ipsj.ixsq.nii.ac.jp:00027646,
 author = {葛毅 and 阿部, 公輝 and 浜田, 穂積 and Takeshi, Katsu and KÔKi, Abe and Hozumi, Hamada},
 issue = {2(1999-SLDM-094)},
 month = {Jan},
 note = {本論文では，URR(Universal Representation of Real numbers)を用いた32ビット浮動小数点乗算回路のIEEE規格との比較とVLSIへの実装について述べる．URRとは浮動小数点数値表現法の一つである．URRは指数部と仮数部を可変長とすることで，IEEE規格に比べて遥かに大きな値や小さな値を表現することを可能としている．しかし，可変長であることから指数部と仮数部の分離／結合処理を行う回路を必要とする．本論文ではURRを実装する際の回路量を評価している．主に次について述べる．(1)URRを用いた浮動小数点乗算回路の構成と分離／結合を行う回路構成の詳細な検討．(2)各構成要素の最適化．(3)IEEE規格の浮動小数点乗算回路との比較．IEEE規格との比較の結果，遅延時間で1.66倍，面積で2.52倍となった．なお，加算回路では遅延時間で1.68倍，面積で2.44倍となった．また，設計した乗算回路の試作チップを作成した．試作チップの主な製造条件は，CMOS0.6μm，4.5mm角である．設計はVerilog-HDLで行い，論理合成にDesign Compiler (Synopsys社)，配置配線にAquariusXO (Avanti社)を使用した．, In this paper we describe the design and VLSI implementation of a 32 bit floating-point multiplier where numbers are represented in an internal form named URR(Universal Representation of Real numbers) by the inventor. With exponential and mantissa parts of variable lengths, URR allows representation of much larger and smaller values than the IEEE standard. The variable length property, however, necessitates separation and combination of the exponential and mantissa parts. We investigate the cost of implementing URR by (1) designing a 32 bit multiplier with circuits for the separation and combination, (2) optimizing the components, and (3) comparing the results with IEEE standard implementation. The investigation reveals that the circuit complexity of URR multiplier is 1.66 times in delay and 2.52 times in area compared with that of IEEE multiplier. The costs of URR adder are also lnvestigated in the same way, and found to be 1.68 and 2.44 for delay and area, respectively, taking IEEE adder's costs as the units. We realized the URR multiplier in a 4.5mm square VLSI chip with CMOS 0.6μm fabrication rule. The design tools used are Verilog-HDL for description, Design Compiler for synthesis, and AquariusXO for placement and routing.},
 title = {URRを用いた浮動小数点乗算回路のVLSIへの実装と評価},
 year = {2000}
}