{"updated":"2025-01-22T18:28:53.761093+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00027558","sets":["1164:2036:2078:2079"]},"path":["2079"],"owner":"1","recid":"27558","title":["2入力論理セルを有するPLAのための論理合成手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2001-11-28"},"_buckets":{"deposit":"e45e00fa-fd93-4516-b7cc-1a6d767c56c0"},"_deposit":{"id":"27558","pid":{"type":"depid","value":"27558","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"2入力論理セルを有するPLAのための論理合成手法","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"2入力論理セルを有するPLAのための論理合成手法"},{"subitem_title":"Logic Synthesis for PLA with 2 - input Logic Elements","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2001-11-28","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京大学大学院工学系研究科電子工学専攻"},{"subitem_text_value":"東京大学大学院工学系研究科電子工学専攻"},{"subitem_text_value":"東京大学大学院工学系研究科電子工学専攻"},{"subitem_text_value":"東京大学大規模集積システム設計教育研究センター"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Department of Electronic Engineering, University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"Department of Electronic Engineering, University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"Department of Electronic Engineering, University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"VLSI Design and Education Center, University of Tokyo","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/27558/files/IPSJ-SLDM01103016.pdf"},"date":[{"dateType":"Available","dateValue":"2003-11-28"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM01103016.pdf","filesize":[{"value":"982.1 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"d2616767-462f-4a05-ba25-982feefe5b16","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2001 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"吉田, 浩章"},{"creatorName":"山岡, 寛明"},{"creatorName":"池田, 誠"},{"creatorName":"浅田, 邦博"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Hiroaki, Yoshida","creatorNameLang":"en"},{"creatorName":"Hiroaki, Yamaoka","creatorNameLang":"en"},{"creatorName":"Makoto, Ikeda","creatorNameLang":"en"},{"creatorName":"Kunihiro, Asada","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本論文では、２入力論理セルを有する PLA のため論理合成手法を提案する。２入力論理セルを有する PLA は、ラッチ型センスアンプおよび寄生容量間の電荷分配を利用することによって高速動作および低消費電力を実現している。さらに、従来の AND/OR 平面における AND/IR セルを任意の２入力論理セルに置き換えられることが可能になっている。よって従来の PLA に比べて論理関数を効率的に実現することができる。提案手法は、新たな２入力論理関数抽出手法に基づいており、また多値論理合成やファクタリングといった既存のアルゴリズムを最大限利用しているため、簡単な実装および高速計算を可能にしている。また提案手法の例題に対する計算機実験の結果を示す。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In this paper, we present a new logic synthesis method for PLA with 2-input logic elements. A PLA with 2-input logic elements can achieve low-power dissipation and high-speed operation by using latch sense-amplifiers and a charge sharing scheme. In addition, arbitrary 2-input logic function is conveniently implemented in place of the conventional AND/OR planes. Therefore it can realize some classes of logic functions in a smaller circuit area. Since the proposed method makes full use of the existing multiple-valued logic minimization algorithms along with a new logic extraction technique for 2-input functions, it can be easily implemented and can handle practical circuits. The method has been implemened and the experimental results are presented.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"104","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"99","bibliographicIssueDates":{"bibliographicIssueDate":"2001-11-28","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"117(2001-SLDM-103)","bibliographicVolumeNumber":"2001"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"created":"2025-01-18T22:57:53.163042+00:00","id":27558,"links":{}}