{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00027508","sets":["1164:2036:2073:2076"]},"path":["2076"],"owner":"1","recid":"27508","title":["リアルタイムシステムのためのハードウェアコンパイレーション技術"],"pubdate":{"attribute_name":"公開日","attribute_value":"2002-03-04"},"_buckets":{"deposit":"69be05e4-8162-4a33-b384-d7a426d7ae52"},"_deposit":{"id":"27508","pid":{"type":"depid","value":"27508","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"リアルタイムシステムのためのハードウェアコンパイレーション技術","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"リアルタイムシステムのためのハードウェアコンパイレーション技術"},{"subitem_title":"Hardware Compilation Techniques for Real - Time Systems","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2002-03-04","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"日本セロックシカ株式会社"},{"subitem_text_value":"日本セロックシカ株式会社"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Chief Science Officer, Celoxica Ltd.","subitem_text_language":"en"},{"subitem_text_value":"SVP Technology, Celoxica Ltd.","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/27508/files/IPSJ-SLDM01105001.pdf"},"date":[{"dateType":"Available","dateValue":"2010-05-25"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM01105001.pdf","filesize":[{"value":"137.2 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"542ccb34-6654-40ab-aeec-6e3522de1b4d","displaytype":"detail","licensetype":"license_note","license_note":"本記事の著作権は著者に帰属します． "}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"イアン・ページ"},{"creatorName":"マット・ニューマン"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Ian, Page","creatorNameLang":"en"},{"creatorName":"Mat, Newman","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"今日リアルタイムシステムには設計者が考慮しなければならないプロセッシングコンポーネント（CPU  DSP  FPGA/PLD および ASIC）の選択肢が多くある。システムが複雑になればなるほど、プロジェクトの成功は、開発ツールやランタイム環境に依存する。本稿では、Handel-C言語とDK１による、生産性向上、かつ、複雑なアルゴリズムのFPGA/PLDへのダイレクトな実装、実行を可能にする新しいアプローチを紹介する。これを、組込みシステム内のビデオ暗号化アルゴリズムのハードウェア加速例を用いて説明する。従来の手法と比べて設計時間が大幅に短縮し、決められた時間でより多くのアーキテクチャ構想が可能になるため、デザインもより改善されたものになった。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Many choices of processing components face the designer of today's real-time systems, including CPU, DSP, FPGA, and ASIC. With such systems increasing in complexity it is often the development tools and runtime environments that make or break a project. This paper presents Handel-C and DK1 which provide a new approach to rapid design that allows application specialists (software or hardware professionals) to increase their productivity and implement and execute algorithms directly on FPGA silicon. As design is so much faster than conventional methodologies, it is routinely possible to investigate many more architectural possibilities within a fixed design timeframe and so produce improved designs. This is illustrated using an evaluation project where hardware acceleration of a video encryption processing bottleneck was implemented using these tools and the subsequent throughput improvement assessed.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"8","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2002-03-04","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"18(2001-SLDM-105)","bibliographicVolumeNumber":"2002"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":27508,"updated":"2025-01-22T18:29:42.070926+00:00","links":{},"created":"2025-01-18T22:57:50.955810+00:00"}