{"id":27392,"updated":"2025-01-22T18:34:19.740689+00:00","links":{},"created":"2025-01-18T22:57:45.834521+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00027392","sets":["1164:2036:2067:2068"]},"path":["2068"],"owner":"1","recid":"27392","title":["高速Fourier変換を用いた多倍長乗算器の設計と評価およびVLSIへの実装"],"pubdate":{"attribute_name":"公開日","attribute_value":"2003-11-27"},"_buckets":{"deposit":"298d3276-97e4-4d62-8cbe-c63b3af12bf8"},"_deposit":{"id":"27392","pid":{"type":"depid","value":"27392","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"高速Fourier変換を用いた多倍長乗算器の設計と評価およびVLSIへの実装","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"高速Fourier変換を用いた多倍長乗算器の設計と評価およびVLSIへの実装"},{"subitem_title":"Hardware Design and Evaluation of Multidigit FFT multiplier and Its VLSI Implementation","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2003-11-27","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"電気通信大学　電気通信学研究科"},{"subitem_text_value":"電気通信大学　電気通信学研究科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Department of Computer Science, The University of Electro - Communications","subitem_text_language":"en"},{"subitem_text_value":"Department of Computer Science, The University of Electro - Communications","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/27392/files/IPSJ-SLDM03112046.pdf"},"date":[{"dateType":"Available","dateValue":"2005-11-27"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM03112046.pdf","filesize":[{"value":"521.0 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"c745a9d8-8831-419d-ade2-1693b4c15b31","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2003 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"矢崎俊志"},{"creatorName":"阿部, 公輝"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Syunji, Yasaki","creatorNameLang":"en"},{"creatorName":"Koki, Abe","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"円周率計算や暗号などの分野において，数千桁におよぶ多倍長乗算が必要になる場面がある．多倍長乗算を高速に行うためには，FFTを応用した乗算アルゴリズムが用いられる．本論文ではFFT乗算ハードウェア実装について述べる．まず，演算器の構成法に存在する選択肢のいくつかに関して，コストと性能をもとに検討する。さらに、ソフトウェア実装との性能比較を行い，ハードウェア実装の有用性を示す．0.18μｍテクノロジを用いて，浮動小数点データ表現形式を16bitにした小型のFFT乗算器を2.8ｍｍ角のチップに実装した.2^16桁の計算が可能な64bitデータ表現FFT乗算器は，10ｍｍ角程度の現実的なチップサイズで実装可能であるが分かった．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Multiplication of multidigit numbers ranging thousands digits is required in many applications such as calculation of π, cipher, etc. Multidigit multiplication is efficiently by FFT algorithms. In this paper we present a hardware design of FFT multiplication. First, we examine several alternatives in organizing the multiplier based on their costs required and performance obtained. Next we demonstrate the usefulness of the hardware implementation by comparing the performance with software implementation. We further present a VLSI realization of a small scale FFT multiplier on a 2.8mm square chip using CMOS 0.18um technology, using a 16bit data representation in floating point multiplication. The FFT multiplier using 64 bit data representation which enables 2^16 multiplication was found to be implemented on a chip of about 10mm square.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"288","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"283","bibliographicIssueDates":{"bibliographicIssueDate":"2003-11-27","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"120(2003-SLDM-112)","bibliographicVolumeNumber":"2003"}]},"relation_version_is_last":true,"weko_creator_id":"1"}}