{"updated":"2025-01-22T18:33:51.471235+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00027376","sets":["1164:2036:2067:2068"]},"path":["2068"],"owner":"1","recid":"27376","title":["CMOS論理セルレイアウトの網羅的生成による製造時の配線欠陥最小化手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2003-11-27"},"_buckets":{"deposit":"c46661d0-8410-457f-96d9-0a85ef5952d2"},"_deposit":{"id":"27376","pid":{"type":"depid","value":"27376","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"CMOS論理セルレイアウトの網羅的生成による製造時の配線欠陥最小化手法","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"CMOS論理セルレイアウトの網羅的生成による製造時の配線欠陥最小化手法"},{"subitem_title":"Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2003-11-27","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京大学大学院工学系研究科"},{"subitem_text_value":"東京大学大学院工学系研究科／東京大学大規模集積システム設計教育研究センター（VDEC）"},{"subitem_text_value":"東京大学大学院工学系研究科／東京大学大規模集積システム設計教育研究センター（VDEC）"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Dept. of Electronic Engineering, University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"Dept. of Electronic Engineering, University of Tokyo/VLSI Design and Education Center (VDEC), University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"Dept. of Electronic Engineering, University of Tokyo/VLSI Design and Education Center (VDEC), University of Tokyo","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/27376/files/IPSJ-SLDM03112030.pdf"},"date":[{"dateType":"Available","dateValue":"2005-11-27"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM03112030.pdf","filesize":[{"value":"506.2 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"feaa592b-f269-42e3-844d-985fb11b7e9b","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2003 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"飯塚, 哲也"},{"creatorName":"池田, 誠"},{"creatorName":"浅田, 邦博"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Tetsuya, Iizuka","creatorNameLang":"en"},{"creatorName":"Makoto, Ikeda","creatorNameLang":"en"},{"creatorName":"Kunihiro, Asada","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本稿では，最小幅のCMOS論理セルレイアウトを網羅的に生成することにより，製造時に配線に欠陥が発生する確率の最も小さいレイアウトを得る手法を提案する．本手法では製造時に発生するスポット上の欠陥(Spot Defect)により二つのセル内配線が短絡する確率を，その欠陥の大きさの分布と，欠陥がそこに発生することにより短絡を引き起こす領域(Critucal Area)の終端や角での効果を考慮に入れ，それをコスト関数として用いる．これを用いることにより，網羅的に生成した最小幅のセルレイアウトから配線の短絡が最も起きにくいレイアウトを選びだすことが可能となる．レイアウト生成においては，充足可能性判定を用いた手法[1]を利用して可能な幅最小のトランジスタ配置を全て生成し，それら全てに対してセル内配線に特化した網羅的配線手法を適用することにより可能なセルレイアウトパターンを全て生成する．本手法をトランジスタ数14までのCMOS論理回路に適用することにより，配線長最小の解を選び出した場合と比較して配線の短絡の発生率を約15％削減できる事を示した．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This paper proposes am exact cell layout synthesis technique to minimize the probability of wiring faults due to spot defects. We modeled the probability of faults on intra-cell routings with considering the spot defects size distribution and the end effect of critical areas. By using the model as a cost function, we comprehensively generate the minimum width layout of CMOS logic cells and select the optimum layouts. Our comprehensive cell synthesis method utilizes the procedure [1] to generate all possible minimum-width transistor placements and applies the comprehensive intro-cell routing to each generated placement considering the constraints characteristic of standard-cell layouts. Experimental results show that our technique reduces about 15% of the fault probabilities compared with the wire-length-minimum layouts for CMOS logic circuits which have up to 14 transistors.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"191","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"187","bibliographicIssueDates":{"bibliographicIssueDate":"2003-11-27","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"120(2003-SLDM-112)","bibliographicVolumeNumber":"2003"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"created":"2025-01-18T22:57:45.129917+00:00","id":27376,"links":{}}