{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00027288","sets":["1164:2036:2061:2063"]},"path":["2063"],"owner":"1","recid":"27288","title":["高コード効率と低レイテンシ処理を実現した自動車制御・民生・産業機器向けコントローラ用CPUコアの開発"],"pubdate":{"attribute_name":"公開日","attribute_value":"2004-10-22"},"_buckets":{"deposit":"2f498e3f-553e-421a-9c4b-67752fccd603"},"_deposit":{"id":"27288","pid":{"type":"depid","value":"27288","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"高コード効率と低レイテンシ処理を実現した自動車制御・民生・産業機器向けコントローラ用CPUコアの開発","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"高コード効率と低レイテンシ処理を実現した自動車制御・民生・産業機器向けコントローラ用CPUコアの開発"},{"subitem_title":"Small-Code-Size and Low-Latency Microcontroller core for Automotive, Industrial, and PC-Peripheral Applications","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2004-10-22","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"株式会社　日立製作所　中央研究所"},{"subitem_text_value":"株式会社　ルネサステクノロジ"},{"subitem_text_value":"株式会社　日立製作所　日立研究所"},{"subitem_text_value":"株式会社　日立製作所　日立研究所"},{"subitem_text_value":"株式会社　ルネサステクノロジ"},{"subitem_text_value":"株式会社　ルネサステクノロジ"},{"subitem_text_value":"株式会社　ルネサステクノロジ"},{"subitem_text_value":"株式会社　ルネサステクノロジ"},{"subitem_text_value":"株式会社　日立製作所　中央研究所"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Central Research Laboratory, Hitachi Ltd.","subitem_text_language":"en"},{"subitem_text_value":"Renesas Technology Corp.","subitem_text_language":"en"},{"subitem_text_value":"Hitachi Research Laboratory, Hitachi Ltd.","subitem_text_language":"en"},{"subitem_text_value":"Hitachi Research Laboratory, Hitachi Ltd.","subitem_text_language":"en"},{"subitem_text_value":"Renesas Technology Corp.","subitem_text_language":"en"},{"subitem_text_value":"Renesas Technology Corp.","subitem_text_language":"en"},{"subitem_text_value":"Renesas Technology Corp.","subitem_text_language":"en"},{"subitem_text_value":"Renesas Technology Corp.","subitem_text_language":"en"},{"subitem_text_value":"Central Research Laboratory, Hitachi Ltd.","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/27288/files/IPSJ-SLDM04116018.pdf"},"date":[{"dateType":"Available","dateValue":"2006-10-22"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM04116018.pdf","filesize":[{"value":"928.1 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"9f993644-a236-46fc-a904-42f401a983a3","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2004 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"勝, 康夫"},{"creatorName":"竹内, 誠二"},{"creatorName":"安部, 雄一"},{"creatorName":"山田, 弘道"},{"creatorName":"平柳, 和也"},{"creatorName":"冨田, 明彦"},{"creatorName":"萩原, 今朝巳"},{"creatorName":"片岡, 健"},{"creatorName":"志村, 隆則"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Sugure, Yasuo","creatorNameLang":"en"},{"creatorName":"Seiji, Takeuchi","creatorNameLang":"en"},{"creatorName":"Yuichi, Abe","creatorNameLang":"en"},{"creatorName":"Hiromichi, Yamada","creatorNameLang":"en"},{"creatorName":"Kazuya, Hirayanagi","creatorNameLang":"en"},{"creatorName":"Akihiko, Tomita","creatorNameLang":"en"},{"creatorName":"Kesami, Hagiwara","creatorNameLang":"en"},{"creatorName":"Takeshi, Kataoka","creatorNameLang":"en"},{"creatorName":"Takanori, Shimura","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"高コード効率と低レイテンシの命令および割り込み処理を実現した、自動車制御・民生・産業機器向け32ビット組込みRISCコントローラCPUコアを開発した。本コアは，200MHz動作時に360MIPS 400MFLOPSの性能を達成した。高コード効率の実現のため、新規命令の追加とCコンパイラ改善により、コード効率が従来の約75％に改善した。また、低レイテンシの命令処理のために、パイプラインの段数を5段あるいは最小3段に抑えた2並列スーパスカラ方式などを採用することで、サイクル性能が従来の約1.8倍向上した。更に、レジスタバンクとスーパスカラ構造に最適化したレジスタ読み出しパスを利用することで、割り込み例外処理とレジスタ退避処理の並列実行が可能となった。その結果、割り込み応答時間が従来の37サイクルから6サイクルまで大幅に短縮できた。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"A 32-bit embedded RISC microcontroller core targeted for automotive, industrial, and PC-peripheral applications has been developed to offer the smaller code size, lower-latency instruction and interrupt processing. The core achieved 360MIPS and 400MFLOPS at 200MHz measured using Dhrystone 1.1. For smaller code size, new instructions have been added to the instruction set. These new instructions, as well as an enhanced C compiler, produce object files about 25% smaller than those for a previous designed core. A dual-issue superscalar structure consisting of three- or five-stage pipelines provides instruction processing with low latency. The cycle performance is an average of 1.8 times faster than the previous designed core. The superscalar structure and the register bank are used to save CPU registers to the resister bank in parallel when executing interrupt processing. This structure significantly improves interrupt response time from 37 cycles to 6 cycles.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"104","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"99","bibliographicIssueDates":{"bibliographicIssueDate":"2004-10-22","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"102(2004-SLDM-116)","bibliographicVolumeNumber":"2004"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":27288,"updated":"2025-01-22T18:36:21.440240+00:00","links":{},"created":"2025-01-18T22:57:41.241359+00:00"}