{"created":"2025-01-18T22:57:40.933935+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00027281","sets":["1164:2036:2061:2063"]},"path":["2063"],"owner":"1","recid":"27281","title":["0.18μmプロセスによる差分光再構成型ゲートアレイ"],"pubdate":{"attribute_name":"公開日","attribute_value":"2004-10-21"},"_buckets":{"deposit":"7145d12d-ede8-46b5-a0d5-730c7a5430cb"},"_deposit":{"id":"27281","pid":{"type":"depid","value":"27281","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"0.18μmプロセスによる差分光再構成型ゲートアレイ","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"0.18μmプロセスによる差分光再構成型ゲートアレイ"},{"subitem_title":"An Optically Differential Reconfigurable Gate Array","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2004-10-21","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"九州工業大学　情報工学部"},{"subitem_text_value":"九州工業大学　情報工学部"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Faculty of Computer Science and Systems Engineering, Kyushu Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Computer Science and Systems Engineering, Kyushu Institute of Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/27281/files/IPSJ-SLDM04116011.pdf"},"date":[{"dateType":"Available","dateValue":"2006-10-21"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM04116011.pdf","filesize":[{"value":"922.3 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"5513b73e-b3cf-4591-956e-c9a0a61ab19c","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2004 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"渡邊, 実"},{"creatorName":"小林, 史典"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Minoru, Watanabe","creatorNameLang":"en"},{"creatorName":"Fuminori, Kobayashi","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"差分光再構成型ゲートアレイは，FPGA(Field Programmable Gate Array)の一種であるが，回路情報を電気的に書き込むFPGAとは異なり，光学的な書き込みを可能にしたデバイスである．これまでに0.35μmプロセスを用いた差分光再構成型ゲートアレイを開発済みであるが，本稿では，さらに高密度実装した0.18μm高密度差分光再構成型ゲートアレイの設計例について示す．この設計では7.82nm^2のチップに，4個の論理ブロック，5個のスイッチング・マトリックス，16ビットのI/Oビットを実装した．本稿では，再構成回路部，ゲートアレイ部の実装について述べ，受講部に関しては実験結果も示す．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This paper presents the design of a high-density optically differential reconfigurable gate array (ODRGA using a 0.18μm - 5 Metal CMOS process technology. ODRGA is a type of Field Programmable Gate Arrays (FPGAs). However, unlike conventional FPGAs, ODRGAs are reconfigured optically using an external optical system. Although ODRGAs have already been fabricated using a 0.35μm - 3 Metal CMOS process technology, their gate-density remains unsatisfactory. For that reason, a new ODRGA-VLSI chip with four logic blocks, five switching matrices, and 16 I/O bits was fabricated on a 7.82mm^2 chip using more advanced process technology. This paper presents the detailed design of a fabricated ODRGA-VLSI chip, the optical reconfiguration circuit, the gate array structure, the CAD layout, and an ODRGA-VLSI chip mounted on an estimation board. This study also includes experimental results regarding the reconfiguration period.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"66","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"61","bibliographicIssueDates":{"bibliographicIssueDate":"2004-10-21","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"102(2004-SLDM-116)","bibliographicVolumeNumber":"2004"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":27281,"updated":"2025-01-22T18:36:09.100508+00:00","links":{}}