{"id":27236,"updated":"2025-01-22T18:37:03.763032+00:00","links":{},"created":"2025-01-18T22:57:38.895873+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00027236","sets":["1164:2036:2061:2062"]},"path":["2062"],"owner":"1","recid":"27236","title":["高速トランジスタ配置を用いたセル内寄生見積もり手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2004-12-02"},"_buckets":{"deposit":"91372efa-185d-4265-af5d-eddb396f2560"},"_deposit":{"id":"27236","pid":{"type":"depid","value":"27236","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"高速トランジスタ配置を用いたセル内寄生見積もり手法","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"高速トランジスタ配置を用いたセル内寄生見積もり手法"},{"subitem_title":"Accurate Pre - layout Estimation of Intra - cell Parasitics Using Fast Transistor - level Placement","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2004-12-02","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京大学　大学院　工学系研究科　電子工学専攻"},{"subitem_text_value":"Zenasis Technologies  Inc."},{"subitem_text_value":"Zenasis Technologies  Inc."},{"subitem_text_value":"東京大学　大規模集積システム設計教育研究センター（VDEC）"},{"subitem_text_value":"東京大学　大規模集積システム設計教育研究センター（VDEC）"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Department of Electronic Engineering, University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"Zenasis Technologies, Inc.","subitem_text_language":"en"},{"subitem_text_value":"Zenasis Technologies, Inc.","subitem_text_language":"en"},{"subitem_text_value":"VLSI Design and Education Center (VDEC), University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"VLSI Design and Education Center (VDEC), University of Tokyo","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/27236/files/IPSJ-SLDM04117014.pdf"},"date":[{"dateType":"Available","dateValue":"2006-12-02"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM04117014.pdf","filesize":[{"value":"812.0 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"e291e305-272b-407a-90dd-7454f3db65a9","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2004 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"吉田, 浩章"},{"creatorName":"Kaushik, De"},{"creatorName":"Vamsi, Boppana"},{"creatorName":"池田, 誠"},{"creatorName":"浅田, 邦博"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Hiroaki, Yoshida","creatorNameLang":"en"},{"creatorName":"Kaushik, De","creatorNameLang":"en"},{"creatorName":"Vamsi, Boppana","creatorNameLang":"en"},{"creatorName":"Makoto, Ikeda","creatorNameLang":"en"},{"creatorName":"Kunihiro, Asada","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"最近我々は回線のトポロジ解析に基づいたセル内の寄生見積もり手法を提案した[1]．この手法は簡単なスタンダードセルに対しては有効であることが示されているが，特に複雑なセルに対してはその制度は十分ではない．また簡単なセルに対しても，高い精度を得るためには慎重な校正を必要となっている．これらの問題を解決するため，本論文では非常に高速なトランジスタ配置手法を用いることによって，校正を行うことなく，複雑なセルに対しても正確な寄生見積もりを可能とする手法を提案する．最後に提案手法の例題に対する計算機実験の結果を示し，本手法の妥当性を示す．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Recently we proposed a pre-layout estimation method of intra-cell parasitics based on topology analysis[1]. Although the paper showed that the parasitics inside simple cells could be estimated very accurately, it performs a poor estimation on complex cells. Additionally, even for such simple cells, it requires a deliberate calibration to obtain accurate estimates. To overcome these draw backs, this paper proposes a new estimation method based on a fast transistor-level placement algorithm. Our experiment on an industrial standard cell library demonstrates the validity of the new method.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"82","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"77","bibliographicIssueDates":{"bibliographicIssueDate":"2004-12-02","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"122(2004-SLDM-117)","bibliographicVolumeNumber":"2004"}]},"relation_version_is_last":true,"weko_creator_id":"1"}}