A Cost - effective Technique to Mitigate Soft Errors in Logic Circuits

• Item type: SIG Technical Reports(1)
• 公開日: 2004-12-01
• タイトル: A Cost - effective Technique to Mitigate Soft Errors in Logic Circuits
• タイトル / 言語: en
• タイトル: A Cost - effective Technique to Mitigate Soft Errors in Logic Circuits
• 言語: jpn
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_18gh
• 資源タイプ: technical report
• 著者所属: Graduate School of Information Science and Technology The University of Tokyo
• 著者所属: Graduate School of Information Science and Technology The University of Tokyo
• 著者所属: Graduate School of Information Science and Technology The University of Tokyo
• 著者所属: Graduate School of Information Science and Technology The University of Tokyo
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science and Technology, The University of Tokyo
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science and Technology, The University of Tokyo
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science and Technology, The University of Tokyo
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science and Technology, The University of Tokyo
• 著者名: LuongD.HUNG; Masanori, TAKADA; Yi, GE; Shuichi, SAKAI
• 著者名(英): Luong, D.Hung; Masanori, Takada; Yi, Ge; Shuichi, Sakai
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: The soft error rates (SER) in logic circuits increase quickly as devices scale. Existing techniques to mitigate soft errors in logic circuits often incur large overheads. In this work we propose a 'lightweight' technique that detects soft errors in logic circuits utilizing the concept of temporal sampling. The technique adds some modifications to the conventional pipeline to allow data to be sampled twice in time and compared for integrity. The area power and timing overheads of modifying a 32-bit multiplier to support the technique are respectively 19.3% 7.6% and 6.4%. Comparing to existing soft error detection circuit techniques our technique incurs lower overheads The technique is also applicable in scaled process technologies.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: The soft error rates (SER) in logic circuits increase quickly as devices scale. Existing techniques to mitigate soft errors in logic circuits often incur large overheads. In this work, we propose a 'lightweight' technique that detects soft errors in logic circuits, utilizing the concept of temporal sampling. The technique adds some modifications to the conventional pipeline to allow data to be sampled twice in time and compared for integrity. The area, power, and timing overheads of modifying a 32-bit multiplier to support the technique are respectively 19.3%, 7.6%, and 6.4%. Comparing to existing soft error detection circuit techniques, our technique incurs lower overheads, The technique is also applicable in scaled process technologies.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AA11451459
• 書誌情報: 情報処理学会研究報告システムLSI設計技術（SLDM）; 巻 2004, 号 122(2004-SLDM-117), p. 31-36, 発行日 2004-12-01
• Notice: SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc.
• 出版者 / 言語: ja
• 出版者: 情報処理学会