@techreport{oai:ipsj.ixsq.nii.ac.jp:00027227,
 author = {森本, 薫夫 and 永田, 真 and 瀧, 和男 and Masao, Morimoto and Makoto, Nagata and Kazuo, Taki},
 issue = {122(2004-SLDM-117)},
 month = {Dec},
 note = {ASDDL (Asymmetric Slope Differential Dynamic Logic)とASD-CMOS(Asymmetric Slope Differential CMOS)は信号の立上り遷移と立下り遷移に要する時間を意図的に非対称とすることで高速化を図った二線式論理回路である．ASDDLはダイナミック回路，ASD-CMOSはスタティック回路であり，クロック信号を用いずに回路のプリチャージを制御するため，従来のダイナミック回路よりも小面積，低消費電力を実現できる．0.18-μmプロセスによるシミュレーション結果では，ASDDLとASD-CMOS乗算器の遅延時間はそれぞれ1.82nsec，1.78nsecであり，CMOSよりも高速動作が可能なダイナミック回路であるDCVS?DOMINOに比べて96％，94％であった．また，面積はDCVS-DOMINOの92％，97％となり，それにより消費電力はそれぞれ20％，2％削減した．さらに0.13-μmプロセスで試作したテストチップでは，電源電圧1.2VでのASD-CMOS乗算器の遅延時間は1.57nsecであり，正常な動作を確認することができた．, Differential logic circuits with asymmetric signal transition surpass the highest speed that conventional CMOS logic circuits can achieve, resulting from deeply shortened rise time along with reasonably slowed fall time. ASD-CMOS (Asymmetric Slope Differential CMOS) is a static logic and ASDDL (Asymmetric Slope Differential Dynamic Logic) is a dynamic logic without per-gate synchronous clock signal, each of which needs two-phase operationas well as differential signaling. ASDDL/ASD-CMOS achieves smaller area and lower power than conventional dynamic circuits. ASDDL and ASD-CMOS 16-bit multipliers in a 0.18-μm CMOS technology demonstrates 1.82 nsec and 1.78 nsec, which corresponds to 96% and 94% of DCVS-DOMINO, respectively. The area was 92% and 97% of that in DCVS-DOMINO implementation, and the power consumption reduces to 20% and 2%, respectively. A prototype ASD-CMOS 16-bit multiplier with built-in test circuitry fabricated in a 0.13-μm CMOS technology operates with the delay time of 1.57 nsec at 1.2V.},
 title = {非対称な信号遷移を用いた高速論理回路方式},
 year = {2004}
}