{"updated":"2025-01-22T18:41:41.973557+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00027109","sets":["1164:2036:2055:2056"]},"path":["2056"],"owner":"1","recid":"27109","title":["セルレイアウトの歩留まり最適化のためのタイミング制約下におけるデコンバクション手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2005-11-30"},"_buckets":{"deposit":"abcd6bf7-06ca-46bd-99b8-f6948df22e51"},"_deposit":{"id":"27109","pid":{"type":"depid","value":"27109","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"セルレイアウトの歩留まり最適化のためのタイミング制約下におけるデコンバクション手法","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"セルレイアウトの歩留まり最適化のためのタイミング制約下におけるデコンバクション手法"},{"subitem_title":"Timing-Driven Celt Layout De-Compaction for Yield Optimization by CriticaI Area Minimization","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2005-11-30","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京大学大学院工学系研究科"},{"subitem_text_value":"東京大学大学院工学系研究科 東京大学大規模集積システム設計教育研究センター（VDEC）"},{"subitem_text_value":"東京大学大学院工学系研究科 東京大学大規模集積システム設計教育研究センター（VDEC）"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Dept. of Electronic Engineering University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"Dept. of Electronic Engineering University of Tokyo,VLSI Design and Education Center (VDEC) University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"Dept. of Electronic Engineering University of Tokyo,VLSI Design and Education Center (VDEC) University of Tokyo","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/27109/files/IPSJ-SLDM05122021.pdf"},"date":[{"dateType":"Available","dateValue":"2007-11-30"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM05122021.pdf","filesize":[{"value":"997.7 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"c11e67cd-63e7-4e3f-b210-50003a116ce1","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2005 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"飯塚, 哲也"},{"creatorName":"池田, 誠"},{"creatorName":"浅田, 邦博"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Tetsuya, IIZUKA","creatorNameLang":"en"},{"creatorName":"Makoto, IKEDA","creatorNameLang":"en"},{"creatorName":"Kunihiro, ASADA","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本稿では歩留まり最適化のためのセルレイアウトのデコンバクション手法を提案する．歩留まりを考慮した論理合成やフィジカル合成などにおいては歩留まりを最適化したセルライプラリが必要不可欠であり，提案手法では元々のセルレイアウトをデコンバクションすることでレイアウトの歩留まりを自動的に最適化する．本手法では，与えられたタイミング制約の下でセルレイアウトのデコンバクシヨンを行う．タイミング制約の記述には，与えられる元々のレイアウトの遅延時間からの，デコンバクションによる遅延の増分を近似計算するモデルを提案し，それを用いる．実験結果から遅延時間の近似が十分な精度を実現していることが示され，またセルの性能と歩留まりのトレードオフカーブが得られることが示された．このようなトレードオフカーブから必要な性能のレイアウトを選び出し，歩留まりを最適化したライブラリとして追加しておくことで，歩留まりを考慮した最適化手法に必要不可欠なライブラリの構築を行うことができる．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This paper proposes a yield optimization method for standard-cells under timing constraints. Yield-aware logic synthesis and physical optimization require yield-enhanced standard cells and the proposed method automatically creates yield-enhanced cell layouts by de-compacting the original cell layout. However, the careless modification of the original layout may degrade its performances severely. Therefore, the proposed method de-compacts the original layout under given timing constraints using a Linear Prograrrming (LP). We develop a new accurate linear delay model which approximates the difference from the original delay and use this model to formulate the timing constraints in the LP. Experimental results show that the proposed method can pick up the yield variants of a cell layout from the trade off curve of cell delay versus critical area and is used to create the yield-enhanced cell library which is essential to realize yield-aware VLSI design flows.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"126","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"121","bibliographicIssueDates":{"bibliographicIssueDate":"2005-11-30","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"121(2005-SLDM-122)","bibliographicVolumeNumber":"2005"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"created":"2025-01-18T22:57:33.255915+00:00","id":27109,"links":{}}