{"created":"2025-01-18T22:57:31.873345+00:00","updated":"2025-01-22T18:42:25.512132+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00027078","sets":["1164:2036:2049:2054"]},"path":["2054"],"owner":"1","recid":"27078","title":["Flex Power FPGAにおけるしきい値制御用バイアス電圧値組合せの最適化について"],"pubdate":{"attribute_name":"公開日","attribute_value":"2006-01-18"},"_buckets":{"deposit":"98c440aa-9cb8-451d-b8b6-c8a5561d703d"},"_deposit":{"id":"27078","pid":{"type":"depid","value":"27078","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"Flex Power FPGAにおけるしきい値制御用バイアス電圧値組合せの最適化について","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Flex Power FPGAにおけるしきい値制御用バイアス電圧値組合せの最適化について"},{"subitem_title":"Optimization of Body Bias Voltage Set for Threshold Voltage Control in Flex Power FPGA","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2006-01-18","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"産業技術総合研究所エレクトロニクス研究部門エレクトロインフォマティクスグループ"},{"subitem_text_value":" 産業技術総合研究所エレクトロニクス研究部門エレクトロインフォマティクスグループ"},{"subitem_text_value":" 産業技術総合研究所エレクトロニクス研究部門エレクトロインフォマティクスグループ"},{"subitem_text_value":" 産業技術総合研究所エレクトロニクス研究部門エレクトロインフォマティクスグループ/明治大学理工学部情報科学科"},{"subitem_text_value":" 産業技術総合研究所エレクトロニクス研究部門エレクトロインフォマティクスグループ"},{"subitem_text_value":" 産業技術総合研究所エレクトロニクス研究部門エレクトロインフォマティクスグループ"},{"subitem_text_value":" 産業技術総合研究所エレクトロニクス研究部門エレクトロインフォマティクスグループ"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Electroinibnnatics Group, Nanoelectronics Research Institute, AJST","subitem_text_language":"en"},{"subitem_text_value":" Electroinibnnatics Group, Nanoelectronics Research Institute, AJST","subitem_text_language":"en"},{"subitem_text_value":" Electroinibnnatics Group, Nanoelectronics Research Institute, AJST","subitem_text_language":"en"},{"subitem_text_value":" Electroinibnnatics Group, Nanoelectronics Research Institute, AJST / Meiji University","subitem_text_language":"en"},{"subitem_text_value":" Electroinibnnatics Group, Nanoelectronics Research Institute, AJST","subitem_text_language":"en"},{"subitem_text_value":" Electroinibnnatics Group, Nanoelectronics Research Institute, AJST","subitem_text_language":"en"},{"subitem_text_value":" Electroinibnnatics Group, Nanoelectronics Research Institute, AJST","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/27078/files/IPSJ-SLDM06123010.pdf"},"date":[{"dateType":"Available","dateValue":"2008-01-18"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM06123010.pdf","filesize":[{"value":"419.8 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"dfee9d52-1bd7-48c9-a404-ea341f2d0941","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2006 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"河並, 崇"},{"creatorName":"日置, 雅和"},{"creatorName":"松本, 洋平"},{"creatorName":"堤, 利幸"},{"creatorName":"中川, 格"},{"creatorName":"関川, 敏弘"},{"creatorName":"小池, 汎平"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Takashi, KAWANAMI","creatorNameLang":"en"},{"creatorName":"Masakazu, HIOKI","creatorNameLang":"en"},{"creatorName":"Yohei, MATSUMOTO","creatorNameLang":"en"},{"creatorName":"Toshiyuki, TSUTSUMI","creatorNameLang":"en"},{"creatorName":"Tadashi, NAKAGAWA","creatorNameLang":"en"},{"creatorName":"Toshihiro, SEKIGAWA","creatorNameLang":"en"},{"creatorName":"Hanpei, KOIKE","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"Flex Power FPGAはトランジスタのしきい値電圧を電気的に制御することにより，高速化と低消費電力化を可能とした新しいアーキテクチャである．本稿では，Flex Power FPGA上で設定する高速トランジスタと低消費電力トランジスタに割り当てる最適なバイアス電圧の組み合わせの検討を行う．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"The Flex Power FPGA is a new FPGA architecture which enabled high speed operation and low power-consumption by controlling threshold voltage of transistors. This paper discusses the optimal threshold voltage set for threshold voltage control in the Flex Power FPGA.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"60","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"55","bibliographicIssueDates":{"bibliographicIssueDate":"2006-01-18","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"4(2006-SLDM-123)","bibliographicVolumeNumber":"2006"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":27078,"links":{}}