{"id":26962,"updated":"2025-01-22T18:46:31.277205+00:00","links":{},"created":"2025-01-18T22:57:26.595438+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00026962","sets":["1164:2036:2043:2048"]},"path":["2048"],"owner":"1","recid":"26962","title":["動的リコンフィギャラブルプロセッサ MuCCRA の実装"],"pubdate":{"attribute_name":"公開日","attribute_value":"2007-01-18"},"_buckets":{"deposit":"eed5465d-a064-4a5b-957d-a7eebb0dd84d"},"_deposit":{"id":"26962","pid":{"type":"depid","value":"26962","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"動的リコンフィギャラブルプロセッサ MuCCRA の実装","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"動的リコンフィギャラブルプロセッサ MuCCRA の実装"},{"subitem_title":"Implementation of Dynamically Reconfigurable Processor MuCCRA","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2007-01-18","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"慶應義塾大学理工学部"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Faculty of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Science and Technology, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Science and Technology, Keio University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/26962/files/IPSJ-SLDM07128017.pdf"},"date":[{"dateType":"Available","dateValue":"2009-01-18"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM07128017.pdf","filesize":[{"value":"479.7 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英晴"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Takuro, NAKAMURA","creatorNameLang":"en"},{"creatorName":"Yohei, HASEGAWA","creatorNameLang":"en"},{"creatorName":"Satoshi, TSUTSUMI","creatorNameLang":"en"},{"creatorName":"Hiroki, MATSUTANI","creatorNameLang":"en"},{"creatorName":"Vasutan, TUNBUNHENG","creatorNameLang":"en"},{"creatorName":"Adepu, PARIMALA","creatorNameLang":"en"},{"creatorName":"Takashi, NISHIMURA","creatorNameLang":"en"},{"creatorName":"Masaru, KATO","creatorNameLang":"en"},{"creatorName":"Shotaro, SAITO","creatorNameLang":"en"},{"creatorName":"Toru, SANO","creatorNameLang":"en"},{"creatorName":"Naomi, SEKI","creatorNameLang":"en"},{"creatorName":"Keiichiro, HIRAI","creatorNameLang":"en"},{"creatorName":"Mao, KAIYI","creatorNameLang":"en"},{"creatorName":"Hideharu, AMANO","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"MuCCRA(Multi-Core Configurable Reconfigurable Architecture)プロジェクトは、コンフィギャラブルな低電力マルチコア動的リコンフォギャラブルプロセッサに関するアーキテクチャ技術をチップレベルから提案、開発、解析することを目的としている。MuCCRA-1 はこの最初のプロトタイプであり、ローム社の0.18μm プロセスを用いて 5mm 角のダイ上に 4x4 の 24bit PE アレイ、乗算器 4、分散メモリ 4 を実装している。単一コアの小規模な構成であるが、コンフィギュレーションの高速化と仮想ハードウェア機構を備えており、コンテキスト数の制約を気にしないでプログラムすることが可能である。PE アレイは典型的なアイランドスタイルの構造を持ち、性能とコストのトレードオフ、電力モデルの構築等に用いることができる。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"MuCCRA(Multi-Core Configurable Reconfigurable Architecture) project aims to establish architectural techniques to develop low-power multi-core configurable dynamically reconfigurable processors. MuCCRA-1, the first prototype chip in the project is implemented with Rohm's 0.18μm CMOS technology. On the 5mm-square die, 4x4 24bits-PE array, 4 multipliers and 4 distributed shared memory modules are mounted. Although it is a small single core, it provides a high speed configuration mechanism and virtual hardware mechanism to enable programming without taking care of the limitation of context number. PE array structure is a typical island-style architecture on which the trade-off between performance, power consumption and cost can be analyzed.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"102","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムLSI設計技術(SLDM)"}],"bibliographicPageStart":"97","bibliographicIssueDates":{"bibliographicIssueDate":"2007-01-18","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"2(2007-SLDM-128)","bibliographicVolumeNumber":"2007"}]},"relation_version_is_last":true,"weko_creator_id":"1"}}