{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00026961","sets":["1164:2036:2043:2048"]},"path":["2048"],"owner":"1","recid":"26961","title":["SoC 埋め込み型プログラマブルロジック ePLX の設計アーキテクチャの検討と回路マッピングの評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"2007-01-18"},"_buckets":{"deposit":"419c8a1f-3709-42c6-b753-05a8bf16d4fd"},"_deposit":{"id":"26961","pid":{"type":"depid","value":"26961","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"SoC 埋め込み型プログラマブルロジック ePLX の設計アーキテクチャの検討と回路マッピングの評価","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"SoC 埋め込み型プログラマブルロジック ePLX の設計アーキテクチャの検討と回路マッピングの評価"},{"subitem_title":"Analysis of design architecture of ePLX (embedded Programmable Logic matriX) and Evaluation of circuit mapping","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2007-01-18","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"立命館大学大学院 理工学研究科"},{"subitem_text_value":"立命館大学 理工学部"},{"subitem_text_value":"立命館大学 理工学部"},{"subitem_text_value":"立命館大学 理工学部"},{"subitem_text_value":"立命館大学大学院 理工学研究科"},{"subitem_text_value":"株式会社 ルネサス テクノロジ"},{"subitem_text_value":"株式会社 ルネサス テクノロジ"},{"subitem_text_value":"株式会社 ルネサス テクノロジ"},{"subitem_text_value":"株式会社 ルネサス テクノロジ"},{"subitem_text_value":"立命館大学大学院 理工学研究科/立命館大学 理工学部"},{"subitem_text_value":"立命館大学大学院 理工学研究科/立命館大学 理工学部"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate school of Science and Engineering, Ritsumeikan University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Science and Engineering, Ritsumeikan University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Science and Engineering, Ritsumeikan University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Science and Engineering, Ritsumeikan University","subitem_text_language":"en"},{"subitem_text_value":"Graduate school of Science and Engineering, Ritsumeikan University","subitem_text_language":"en"},{"subitem_text_value":"Renesas Technology Corp.","subitem_text_language":"en"},{"subitem_text_value":"Renesas Technology Corp.","subitem_text_language":"en"},{"subitem_text_value":"Renesas Technology Corp.","subitem_text_language":"en"},{"subitem_text_value":"Renesas Technology Corp.","subitem_text_language":"en"},{"subitem_text_value":"Graduate school of Science and Engineering, Ritsumeikan University/Faculty of Science and Engineering, Ritsumeikan University","subitem_text_language":"en"},{"subitem_text_value":"Graduate school of Science and Engineering, Ritsumeikan University/Faculty of Science and Engineering, Ritsumeikan University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/26961/files/IPSJ-SLDM07128016.pdf"},"date":[{"dateType":"Available","dateValue":"2009-01-18"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM07128016.pdf","filesize":[{"value":"429.6 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"998d9f3f-951b-4b5e-8aa5-96b5b477c447","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2007 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"菱田, 智雄"},{"creatorName":"石橋, 宏太"},{"creatorName":"木村, 峻"},{"creatorName":"奥野, 直樹"},{"creatorName":"松本, 光崇"},{"creatorName":"中野, 裕文"},{"creatorName":"岩男, 剛宜"},{"creatorName":"奥野, 義弘"},{"creatorName":"有本, 和民"},{"creatorName":"泉, 知論"},{"creatorName":"藤野, 毅"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Tomoo, HISHIDA","creatorNameLang":"en"},{"creatorName":"Kouta, ISHIBASHI","creatorNameLang":"en"},{"creatorName":"Shun, KIMURA","creatorNameLang":"en"},{"creatorName":"Naoki, OKUNO","creatorNameLang":"en"},{"creatorName":"Mitsutaka, MATSUMOTO","creatorNameLang":"en"},{"creatorName":"Hirofumi, NAKANO","creatorNameLang":"en"},{"creatorName":"Takenobu, IWAO","creatorNameLang":"en"},{"creatorName":"Yoshihiro, OKUNO","creatorNameLang":"en"},{"creatorName":"Kazutami, ARIMOTO","creatorNameLang":"en"},{"creatorName":"Tomonori, IZUMI","creatorNameLang":"en"},{"creatorName":"Takeshi, FUJINO","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"近年、少量生産の SoC （システムオンチップ）製造において、マスク費用やレイアウト・検証設計費用などの初期開発費用の増加が大きな問題になっている。FPGA を製品に使用することも行われているが、FPGA は SoC と比較して性能面で劣っており、１チップあたりの製造コストが高いという問題がある。本論文では、SoC 内の一部にプログラマブルロジック ePLX(embedded Programmable Logic matriX)を配置することを提案する。ePLX を用いることにより、SoC 内の回路ブロックで、アプリケーションや顧客に特有の機能は論理を変更することができる。ePLX アーキテクチャはローカルアーキテクチャ（マトリクス状に配置した２入力 LUT と、マトリクス端に配置した FF）とそれらを接続する階層的な配線リソースを有している点に特徴がある。加算器、乗算器、DES 暗号回路などのサンプル回路を ePLX 上でマッピングした結果から、LUT の使用率を議論する。また、HDL コードから ePLX のコンフィグレーションデータを生成する自動設計フローを紹介し、その一部として開発している自動ツールを用いたローカルアーキテクチャのマッピング結果を報告する。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Recently, non-recurring engineering costs (NREs), including cost of mask-sets, and engineering design efforts are critical problems in a small-volume SoC(System on a Chip) manufacturing. FPGAs are used for some electrical products, but FPGAs still have lower performance and higher chip-cost than SoC. In this paper, we propose ePLX(embedded Programmable Logic matriX) that is embedded in SoC. Application-specific or customers-specific logic function in SoC can be changed using ePLX. The ePLX architecture is based on the programmable local-clusters, which are composed of two input Look-Up-Table(LUT) matrix and the D-FlipFlops on the matrix side. The hierarchical wiring resources are located between the local-clusters. We demonstrate the ePLX mapping results for sample circuits such as an adder, a multiplier, and a DES encryption circuit, and discuss LUT utilization efficiency. Lastly, we introduce ePLX design flow from HDL code to ePLX configuration data, and experimental results using the mapping tool which is newly-developed for ePLX.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"96","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"91","bibliographicIssueDates":{"bibliographicIssueDate":"2007-01-18","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"2(2007-SLDM-128)","bibliographicVolumeNumber":"2007"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":26961,"updated":"2025-01-22T18:46:29.477470+00:00","links":{},"created":"2025-01-18T22:57:26.551470+00:00"}