{"updated":"2025-01-22T18:47:02.112054+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00026938","sets":["1164:2036:2043:2047"]},"path":["2047"],"owner":"1","recid":"26938","title":["HW/SWコデザインにおける共有アドレス空間を介した統一的なモジュール間インタフェースの実現法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2007-03-16"},"_buckets":{"deposit":"4b41f06d-4e6d-42d5-b01b-ca2ccd6a1d39"},"_deposit":{"id":"26938","pid":{"type":"depid","value":"26938","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"HW/SWコデザインにおける共有アドレス空間を介した統一的なモジュール間インタフェースの実現法","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"HW/SWコデザインにおける共有アドレス空間を介した統一的なモジュール間インタフェースの実現法"},{"subitem_title":"A Hardware Design Method Using Semi-Programmable Reconfigurable Processor","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2007-03-16","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"九州工業大学工学部"},{"subitem_text_value":"九州工業大学工学部"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Faculty of Engineering, Kyushu Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Engineering, Kyushu Institute of Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/26938/files/IPSJ-SLDM07129013.pdf"},"date":[{"dateType":"Available","dateValue":"2009-03-16"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM07129013.pdf","filesize":[{"value":"555.2 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"fec81ad9-b998-444b-a205-3aeffbf38f9f","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2007 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"山脇, 彰"},{"creatorName":"岩根, 雅彦"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Akira, YAMAWAKI","creatorNameLang":"en"},{"creatorName":"Masahiko, IWANE","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"システムレベルデザインにおける抽象的なモジュール間インタフェースは，HW/SWコデザインシステムによって，HWでは専用の入出力制御回路に変換される．ただし，メモリアクセスパタンや必要なデータ量が異なる処理ごとに最適な入出力制御回路を生成することは難しいさらに，メモリレイテンシの隠蔽に対する取り組みはコデザインシステムではあまり考慮されていないそこで、コデザインシステムのハードウェアモジュールとしてセミプログラマブル再構成可能プロセッサ(SPRCP)の導入を提案する．SPRCＰはメモリアクセス用簡易プロセッサ(LSU)と，ハードウェア構成部(EXU)がレジスタを挟んだ構成を持つ．ＥＸＵにとってデータ入出力は単なるレジスタ読み書きであり，柔軟なメモリアクセスはＬＳＵがメモリアクセスプログラムを実行することによって提供される．LSUとEXUは並列に動作するため，処理とメモリアクセスをオーバラップできる．本稿を通して，メモリアクセスを隠蔽できる統一的なSW-HW間，HW-HW間インタフェースを，SPRCＰが提供し得ることを示す．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"On a HW/SW co-design system, generating HW-HW and SW-SW interfaces is important to provide fair performance and hardware size. However, it is difficult to provide each process a specific interface circuit. Also, memory access latency becomes larger relative to the execution time reduced. This paper proposes introducing Semi-Programmable ReConfigurable Processor (SPRCP) to a HW/SW co-design system as a frame work of the hardware module. The SPRCP consists of a load/store unit and a hardware unit. The farmer is a tiny processor for memory access and the latter is a reconfigurable hardware unit. The register file is lies between them and provides the hardware unit an easy systematic interface. Instead of hardware unit, the load/store unit performs the flexible memory access and overlaps the memory accesses and hardware execution to hide memory access latency.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"76","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"71","bibliographicIssueDates":{"bibliographicIssueDate":"2007-03-16","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"27(2007-SLDM-129)","bibliographicVolumeNumber":"2007"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"created":"2025-01-18T22:57:25.535454+00:00","id":26938,"links":{}}