{"id":26853,"updated":"2025-01-22T18:49:38.234387+00:00","links":{},"created":"2025-01-18T22:57:21.789502+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00026853","sets":["1164:2036:2037:2042"]},"path":["2042"],"owner":"1","recid":"26853","title":["並列ボリュームレンダリング・アクセラレータVisAの開発とその予備実装"],"pubdate":{"attribute_name":"公開日","attribute_value":"2008-01-17"},"_buckets":{"deposit":"f4bc003a-564f-4795-b036-ba32120a55b9"},"_deposit":{"id":"26853","pid":{"type":"depid","value":"26853","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"並列ボリュームレンダリング・アクセラレータVisAの開発とその予備実装","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"並列ボリュームレンダリング・アクセラレータVisAの開発とその予備実装"},{"subitem_title":"Development of Parallel Volume Rendering Accelerator VisA and its Preliminary Implementation","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2008-01-17","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"京都大学"},{"subitem_text_value":"京都大学"},{"subitem_text_value":"京都大学"},{"subitem_text_value":"福井大学"},{"subitem_text_value":"京都大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Kyoto University","subitem_text_language":"en"},{"subitem_text_value":"Kyoto University","subitem_text_language":"en"},{"subitem_text_value":"Kyoto University","subitem_text_language":"en"},{"subitem_text_value":"University of Fukui","subitem_text_language":"en"},{"subitem_text_value":"Kyoto University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/26853/files/IPSJ-SLDM08133018.pdf"},"date":[{"dateType":"Available","dateValue":"2010-01-17"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM08133018.pdf","filesize":[{"value":"694.2 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"b58357d6-59c8-407f-ba2b-be9f79100075","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2008 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"川原, 崇宏"},{"creatorName":"三輪, 忍"},{"creatorName":"嶋田, 創"},{"creatorName":"森, 眞一郎"},{"creatorName":"富田, 眞治"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Takahiro, KAWAHARA","creatorNameLang":"en"},{"creatorName":"Shinobu, MIWA","creatorNameLang":"en"},{"creatorName":"Hajime, SHIMADA","creatorNameLang":"en"},{"creatorName":"Shin-ichiro, MORI","creatorNameLang":"en"},{"creatorName":"Shinji, TOMITA","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"我々は並列処理可能なボリュームレンダリング・アクセラレータ『VisA』を開発している．VisAはディスプレイ用汎用インタフェースであるDVI-Dケーブルを通信路として用いた単方向リンクにより，ノード間の画像合成処理とノード内での画像生成処理を統合した細粒度パイプラインを実現している．本稿ではVisAの設計手法と予備実装による評価について述べる．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"We are developing the parallel volume rendering accelerator VisA. VisA communicates with one-way link over DVI-D which is usualy used as a display interface, so it achieves the fine grain pipeline system which integrates both image composition between nodes and image rendering inside a node. This paper describes the design concept of VisA and its preliminary implementation.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"108","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"103","bibliographicIssueDates":{"bibliographicIssueDate":"2008-01-17","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"2(2008-SLDM-133)","bibliographicVolumeNumber":"2008"}]},"relation_version_is_last":true,"weko_creator_id":"1"}}