{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00026838","sets":["1164:2036:2037:2042"]},"path":["2042"],"owner":"1","recid":"26838","title":["FPGAアレイを用いたスケーラブルなReconfigurable HPC"],"pubdate":{"attribute_name":"公開日","attribute_value":"2008-01-16"},"_buckets":{"deposit":"0e0a0462-c61c-4b9b-b30f-a9d4896d4308"},"_deposit":{"id":"26838","pid":{"type":"depid","value":"26838","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"FPGAアレイを用いたスケーラブルなReconfigurable HPC","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"FPGAアレイを用いたスケーラブルなReconfigurable HPC"},{"subitem_title":"Scalable RHPC (Reconfigurable HPC) by using FPGA array","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2008-01-16","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京農工大学工学府"},{"subitem_text_value":"東京農工大学工学府"},{"subitem_text_value":"東京農工大学工学府"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"The Faculty of Technology, Tokyo University of Agriculture and Technology","subitem_text_language":"en"},{"subitem_text_value":"The Faculty of Technology, Tokyo University of Agriculture and Technology","subitem_text_language":"en"},{"subitem_text_value":"The Faculty of Technology, Tokyo University of Agriculture and Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/26838/files/IPSJ-SLDM08133003.pdf"},"date":[{"dateType":"Available","dateValue":"2010-01-16"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM08133003.pdf","filesize":[{"value":"671.4 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"25584452-f8d1-4828-adb1-e7f132b40bd9","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2008 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"飯島, 浩晃"},{"creatorName":"佐藤－輝"},{"creatorName":"関根, 優年"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Hiroaki, IIJIMA","creatorNameLang":"en"},{"creatorName":"Kazuki, SATO","creatorNameLang":"en"},{"creatorName":"Masatoshi, SEKINE","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"大規模演算をスケーラブルに行える基盤として，多数のFPGA同士を相互接続したFPGAアレイが提案されている．我々が提案するFPGAアレイは，大規模FPGAを搭載し，外部10を大量に装備した小型のFPGAカードを，格子状に並べた構成を取る．演算回路を格納するFPGAは，対象問題にあわせて回路を構成することができるため，比較的安価に専用回路を用いた高性能な演算を手に入れることができる．FPGAアレイはPCI型FPGAカード(hwModule)に接続し，hw/sw複合体に組み込むことで容易な制御を目指す．本稿では提案システムによって，差分法によるポアソン方程式の演算を，どれだけ高速に行うことができるかについて予備実験を行った．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"FPGA array that interconnect amang many FPGAs was reported as foundation for large-scale operations. FPGA array we propose in this paper consist of a grid structure by using small FPGA card, which equips with large-scale FPGA and large amount of external IOs. This FPGA can reconfigure the arithmetic circuit to fit the target problem, so get a dedicated circuit for high-performance computing at relatively cheap. FPGA array aims at easy to control by embedding in hw/sw complex through PCI type FPGA card. This paper takes the pilot study how fast proposed system can calculate Poisson's equation by the finite difference method.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"18","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"13","bibliographicIssueDates":{"bibliographicIssueDate":"2008-01-16","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"2(2008-SLDM-133)","bibliographicVolumeNumber":"2008"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":26838,"updated":"2025-01-22T18:49:09.566801+00:00","links":{},"created":"2025-01-18T22:57:21.111389+00:00"}