@techreport{oai:ipsj.ixsq.nii.ac.jp:00026797,
 author = {奥村, 俊介 and 藤原, 英弘 and 井口, 友輔 and 野口, 紘希 and 森田, 泰弘 and 川口, 博 and 吉本, 雅彦 and Shunsuke, Okumura and Hidehiro, Fujiwara and Yusuke, Iguchi and Hiroki, Noguchi and Yasuhiro, Morita and Hiroshi, Kawaguchi and Masahiko, Yoshimoto},
 issue = {38(2008-SLDM-135)},
 month = {May},
 note = {信頼性を動的に変化させることが可能なディペンダブル SRAM を提案する．提案する SRAM は ７ トランジスタ（7T）構成であり，２つの従来 6Ｔ メモリセルを１組として，双方の内部ノードを追加トランジスタで接続する．提案 SRAM は通常モード，高速アクセスモード，そして高信頼性モードの３種類のモードを有する．提案 SRAM の高速アクセスモードでは，従来の 6T SRAM と比較して読出しセル電流が 142％増加し，その結果読出し時のビット線放電時間は 66.3％短縮される．また，高信頼性モードにおいては，Bit error rate（BER）が 2.5x10-2 改善された．面積オーバーヘッドは追加トランジスタに PMOS を用いた場合は 12％である．, We propose a novel dependable SRAM with 7T memory cell pair, and introduce a new concept, “quality of a bit (QoB)” for it. The proposed SRAM has three modes: a typical mode, high-speed mode, and dependable mode, in which the QoB is scalable. That is, the area, speed, reliability, and/or power of one-bit information can be controlled. In the typical mode, assignment of information is as usual as one memory cell has one bit. On the other hand, in the high-speed or dependable mode, one-bit information is stored in two memory cells, which boosts the speed or increases the reliability. In the high speed mode, the cell current is increased by 142％, and bitline discharge time is reduced by 66.3％. Furthermore, in dependable mode, Bit error rate (BER) in proposed SRAM is improved by 2.5x10-2. Compared with the conventional 6T memory cell, the respective area overheads are 30％ and 12％, in the nMOS and pMOS additional cases.},
 title = {高信頼性モードと高速アクセスモードを有するディペンダブル SRAM},
 year = {2008}
}