{"links":{},"id":26753,"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00026753","sets":["1164:2036:2037:2038"]},"path":["2038"],"owner":"1","recid":"26753","title":["高信頼セルによる回路の信頼性評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"2008-11-10"},"_buckets":{"deposit":"f26fa322-cabd-4f0e-9548-3da49f4cfcb4"},"_deposit":{"id":"26753","pid":{"type":"depid","value":"26753","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"高信頼セルによる回路の信頼性評価","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"高信頼セルによる回路の信頼性評価"},{"subitem_title":"Evaluating the reliability of Highly Reliable Cell Circuits","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2008-11-10","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"奈良先端科学技術大学院大学"},{"subitem_text_value":"奈良先端科学技術大学院大学"},{"subitem_text_value":"奈良先端科学技術大学院大学"},{"subitem_text_value":"奈良先端科学技術大学院大学"},{"subitem_text_value":"奈良先端科学技術大学院大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Nara Institute of Science and Technology","subitem_text_language":"en"},{"subitem_text_value":"Nara Institute of Science and Technology","subitem_text_language":"en"},{"subitem_text_value":"Nara Institute of Science and Technology","subitem_text_language":"en"},{"subitem_text_value":"Nara Institute of Science and Technology","subitem_text_language":"en"},{"subitem_text_value":"Nara Institute of Science and Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/26753/files/IPSJ-SLDM08137016.pdf"},"date":[{"dateType":"Available","dateValue":"2010-11-10"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM08137016.pdf","filesize":[{"value":"804.8 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"01876464-2b17-48e8-a043-2cf24ad414b3","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2008 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"堀田, 敬一"},{"creatorName":"中田, 尚"},{"creatorName":"中西, 正樹"},{"creatorName":"山下, 茂"},{"creatorName":"中島, 康彦"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Keiichi, Hotta","creatorNameLang":"en"},{"creatorName":"Takashi, Nakada","creatorNameLang":"en"},{"creatorName":"Masaki, Nakanishi","creatorNameLang":"en"},{"creatorName":"Shigeru, Yamashita","creatorNameLang":"en"},{"creatorName":"Yasuhiko, Nakashima","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"近年のトランジスタ製造によるプロセス微細化によって，トランジスタの故障率の増加が問題となっている．そこで故障率の増加を抑える手法として，高信頼セルを用いて回路を構成する手法が提案されている．高信頼セルは従来セルと比較して耐故障性が高いと考えられている．この耐故障性を定量的に扱うためには，信頼性評価を行う必要がある．信頼性評価手法はいくつか提案されているが，従来手法を用いて高信頼セルの信頼性評価を行う場合，信頼性を正確に評価できない問題が生じる．そこで本論文では，正確な評価を行うためにトランジスタの故障率をもとに回路全体の信頼性を評価する手法を提案する．これにより従来セルと高信頼セルによる回路の信頼性を定量的に評価することが可能になる．提案手法を用いた従来セルと高信頼セルの信頼性の評価実験を行った結果，従来セルと比較して高信頼セルの信頼性がどの程度高いかを定量的に示した．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Recently, the shrinking process causes transistor variation and growth of error rate. Highly Reliable Cells (HRCs) have been proposed to solve these problems. We need to evaluate reliability of them quantitatively, because they are considered to be highly reliable. Although, there have been proposed several methods to evaluate the reliability, they cannot evaluate the reliability of circuits by HRCs accurately. Therefore, in this paper, we propose a new evaluation method for the reliability of circuits based on the fault probability of each transistor. The method can evaluate the reliablity of circuits by HRCs or the CMOS cells. The experimental results show that HRCs are more reliable than the CMOS cells. ","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"96","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムLSI設計技術（SLDM）"}],"bibliographicPageStart":"91","bibliographicIssueDates":{"bibliographicIssueDate":"2008-11-10","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"111(2008-SLDM-137)","bibliographicVolumeNumber":"2008"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"created":"2025-01-18T22:57:17.347512+00:00","updated":"2025-01-22T18:52:35.320392+00:00"}