{"created":"2025-01-18T22:56:39.672989+00:00","updated":"2025-01-22T19:15:54.913972+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00025901","sets":["1164:1867:1906:1909"]},"path":["1909"],"owner":"1","recid":"25901","title":["マルチスレッドアーキテクチャ用データキャッシュ?動的スレッドアソシアティブ方式?の評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"1999-03-04"},"_buckets":{"deposit":"4bc29195-7465-4bcd-bdc7-64fab32eb754"},"_deposit":{"id":"25901","pid":{"type":"depid","value":"25901","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"マルチスレッドアーキテクチャ用データキャッシュ?動的スレッドアソシアティブ方式?の評価","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"マルチスレッドアーキテクチャ用データキャッシュ?動的スレッドアソシアティブ方式?の評価"},{"subitem_title":"An Analysis of A Data Cache Dynamically Thread-Associative for Multithread Architecture","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1999-03-04","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"電気通信大学大学院情報システム学研究科"},{"subitem_text_value":"電気通信大学大学院情報システム学研究科"},{"subitem_text_value":"電気通信大学大学院情報システム学研究科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"The Graduate School of Information Systems, The University of Electro - Communications","subitem_text_language":"en"},{"subitem_text_value":"The Graduate School of Information Systems, The University of Electro - Communications","subitem_text_language":"en"},{"subitem_text_value":"The Graduate School of Information Systems, The University of Electro - Communications","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/25901/files/IPSJ-OS98080017.pdf"},"date":[{"dateType":"Available","dateValue":"2001-03-04"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-OS98080017.pdf","filesize":[{"value":"575.1 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"11"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"2575c707-a879-4d83-97d9-3897e37505fa","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1999 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"山崎, 真矢"},{"creatorName":"本多, 弘樹"},{"creatorName":"弓場, 敏嗣"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Shinya, Yamazaki","creatorNameLang":"en"},{"creatorName":"Hiroki, Honda","creatorNameLang":"en"},{"creatorName":"Toshitsugu, Yuba","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10444176","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本稿では，マルチスレッドプロセッサのキャッシュ構成として，各スレッドで使用できるキャッシュラインをスレッド処理数に応じて制限する動的スレッドアソシアティブ(Dynamically Thread-Associative)方式[1]の評価報告をする。本方式では，従来のセットアソシアティブ方式の置き換え動作を変更しキャッシュ内にスレッド専用領域を確保することで，複数のスレッド間での干渉によって起こるキャッシュミスを低減することが期待できる。シミュレータを用いて本方式の評価を行った結果，本方式により複数スレッド間での干渉を低減できることがわかった。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"We have presented a new replacement algorithm in set-associative cache adapted to multithread architecture. By restricting the replacement candidate blocks to the sub-set in a set that exclusively assigned to each thread, the cache miss rate caused by the interference among threads can be kept low. This paper shows the result of the measurements on the cache simulator.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"102","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムソフトウェアとオペレーティング・システム（OS）"}],"bibliographicPageStart":"97","bibliographicIssueDates":{"bibliographicIssueDate":"1999-03-04","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"21(1998-OS-080)","bibliographicVolumeNumber":"1999"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":25901,"links":{}}