{"id":25899,"updated":"2025-01-22T19:15:51.143786+00:00","links":{},"created":"2025-01-18T22:56:39.582017+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00025899","sets":["1164:1867:1906:1909"]},"path":["1909"],"owner":"1","recid":"25899","title":["オンチップメモリを用いたHPCプロセッサの検討"],"pubdate":{"attribute_name":"公開日","attribute_value":"1999-03-04"},"_buckets":{"deposit":"ebb3324a-a791-4b2d-a611-abecd5df3ae0"},"_deposit":{"id":"25899","pid":{"type":"depid","value":"25899","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"オンチップメモリを用いたHPCプロセッサの検討","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"オンチップメモリを用いたHPCプロセッサの検討"},{"subitem_title":"A study of HPC processor using On - Chip Memory","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1999-03-04","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"筑波大学電子・情報工学系"},{"subitem_text_value":"東京大学工学研究科電気工学"},{"subitem_text_value":"筑波大学電子・情報工学系"},{"subitem_text_value":"東京大学先端科学技術研究センター"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Institute of Information Sciences and Electronics, University of Tsukuba","subitem_text_language":"en"},{"subitem_text_value":"Department of Electrical Engineering, The University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"Institute of Information Sciences and Electronics, University of Tsukuba","subitem_text_language":"en"},{"subitem_text_value":"Research Center for Advanced Science and Technology, University of Tokyo","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/25899/files/IPSJ-OS98080015.pdf"},"date":[{"dateType":"Available","dateValue":"2001-03-04"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-OS98080015.pdf","filesize":[{"value":"626.5 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"11"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"6573ff7b-6f08-40c8-8a92-07f22a5f37a1","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1999 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"近藤, 正章"},{"creatorName":"坂井, 修一"},{"creatorName":"朴, 泰祐"},{"creatorName":"中村, 宏"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Masaaki, Kondo","creatorNameLang":"en"},{"creatorName":"Shuichi, Sakai","creatorNameLang":"en"},{"creatorName":"Taisuke, Boku","creatorNameLang":"en"},{"creatorName":"Hiroshi, Nakamura","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10444176","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本稿では，CPUとメモリをシングルチップ上に融合させたプロセッサ・メモリ混載型LSIについて，特にHPC分野をターゲットにしたアーキテクチャの検討を行なう．プロセッサ・メモリ混載型LSIでは，オンチップメモリに対するアクセスが低レーテンシかつ高バンド幅であるため，性能向上が期待されるが，HPCではワーキングセットが大きく，オンチップメモリにそのすべてが収まりきらないことが多い．ここでは，最初に，HPC用VLSIアーキテクチャとしてオンチップメモリ，オフチップメモリの両者を持つアーキテクチャを考え，その命令セットおよびハードウェア構成の概略を提案する．次に，オンチップ・オフチップ両メモリのスループット，浮動小数点演算器数などをパラメータとして，いくつかのプログラムについての予備実験を行ない，アーキテクチャの諸元を設定する．さらに，Linpackベンチマークプログラムにおける性能予測では，オンチップメモリを用いたブロッキングを行なうことにより，プロセッサ・メモリ混載型LSIで高性能が得られることを確認した．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In this paper, we describe our study of processor-memory intergrated LSI architecture aiming at performance improvement of HPC applications. The memory-integrated processor has low latency and high bandwidth in respect of access to the on-chip memory. In the HPC applications, however, their working sets are too large to fit into the on-chip memory. Therefore we discuss VLSI architecture with both on-chip and off-chip memories, and we propose an outline of extended instructions and hardware. In addition, to decide architectural factors, the performance of some programs are evaluated with on-chip/off-chip memory throughput and number of floating point pipeline units being parameterized. And Linpack benchmark examination shows that memory-integrated processor achieves high performance taking on-chip memory blocking algorithm.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"90","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告システムソフトウェアとオペレーティング・システム（OS）"}],"bibliographicPageStart":"85","bibliographicIssueDates":{"bibliographicIssueDate":"1999-03-04","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"21(1998-OS-080)","bibliographicVolumeNumber":"1999"}]},"relation_version_is_last":true,"weko_creator_id":"1"}}