{"id":25131,"updated":"2025-01-22T19:37:35.513732+00:00","links":{},"created":"2025-01-18T22:56:05.368448+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00025131","sets":["1164:1579:1795:1803"]},"path":["1803"],"owner":"1","recid":"25131","title":["高速演算処理用コプロセサ8087"],"pubdate":{"attribute_name":"公開日","attribute_value":"1981-04-20"},"_buckets":{"deposit":"1b8bed6d-5650-403a-aa8b-90c8987e7db4"},"_deposit":{"id":"25131","pid":{"type":"depid","value":"25131","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"高速演算処理用コプロセサ8087","author_link":["0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"高速演算処理用コプロセサ8087"}]},"item_type_id":"4","publish_date":"1981-04-20","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"インテルジャパン教育センター"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/25131/files/IPSJ-ARC81016003.pdf"},"date":[{"dateType":"Available","dateValue":"1983-04-20"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC81016003.pdf","filesize":[{"value":"1.4 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"e3bd96ee-6051-4550-ba44-ccc1fbaa33aa","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1981 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"鎌田信夫"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"16ビットのマイクロプロセサがかなり一般化し広い分野で応用され始めている。今日市販されている16ビットマイクロプロセサはその命令セット，アドレス空間，マルチプロセサに対する備えなどの点ですでにミニコンと変らない水準にある。しかし入出力制御や浮動小数点演算に対してはこれらのマイクロプロセサは特別なハードウェアを内蔵するまでに至っていない。そこでこのLSI技術の制限の下でシステム全体としての性能向上をはかるべく探られている手法はそれぞれ別パッケージの専用プロセサを用意しいくつかのプロセサ群を組合わせてシステムを構成する方法である。ここではその一例である16ビットcpuと密結合で使用される高速演算処理用プロセサ8087について，その動作，性能について紹介する。","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"8","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告計算機アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"1981-04-20","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"2(1981-ARC-016)","bibliographicVolumeNumber":"1981"}]},"relation_version_is_last":true,"weko_creator_id":"1"}}