{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00024881","sets":["1164:1579:1738:1746"]},"path":["1746"],"owner":"1","recid":"24881","title":["パイプライン処理とプランチ命令"],"pubdate":{"attribute_name":"公開日","attribute_value":"1987-03-13"},"_buckets":{"deposit":"ba147f32-b627-4023-bfa0-85a95ec0e0b5"},"_deposit":{"id":"24881","pid":{"type":"depid","value":"24881","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"パイプライン処理とプランチ命令","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"パイプライン処理とプランチ命令"},{"subitem_title":"BRANCH PREDICTION IN A PIPELINED MICROPROCESSOR","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1987-03-13","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"三菱電機（株）LSI研究所"},{"subitem_text_value":"三菱電機（株）LSI研究所"},{"subitem_text_value":"三菱電機（株）LSI研究所"},{"subitem_text_value":"三菱電機（株）LSI研究所"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"MISTUBISHI ELECTRIC Corporation LSI Research and Development Laboratory","subitem_text_language":"en"},{"subitem_text_value":"MISTUBISHI ELECTRIC Corporation LSI Research and Development Laboratory","subitem_text_language":"en"},{"subitem_text_value":"MISTUBISHI ELECTRIC Corporation LSI Research and Development Laboratory","subitem_text_language":"en"},{"subitem_text_value":"MISTUBISHI ELECTRIC Corporation LSI Research and Development Laboratory","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/24881/files/IPSJ-ARC86044001.pdf"},"date":[{"dateType":"Available","dateValue":"1989-03-13"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC86044001.pdf","filesize":[{"value":"1.2 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"d7431903-25ac-410b-8592-220604caf857","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1987 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"吉田, 豊彦"},{"creatorName":"松尾, 雅仁"},{"creatorName":"上田, 達也"},{"creatorName":"清水, 徹"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Toyohiko, Yoshida","creatorNameLang":"en"},{"creatorName":"Masahito, Matsuo","creatorNameLang":"en"},{"creatorName":"Tatsuya, Ueda","creatorNameLang":"en"},{"creatorName":"Toru, Shimizu","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"我々はオリジナル32ビットマイクロプロセッサの開発にあたり新しいマイクロプロセッサのアーキテクチャに適する各種のパイプライン方式を検討した。パイプライン処理は汎用計算機の歴史の中で高速化技術として最も成功したものの1つである。しかし、パイプライン処理も処理段数が増大するにつれて各種のオーバーヘッドのため処理速度の向上に飽和傾向が現れる。パイプライン処理のオーバーヘッドのなかで最も問題となるのはブランチ命令実行によるパイプラインの乱れである。我々はパイプライン処理におけるブランチ命令のオーバーヘッドをなるべく少なくするため、ブランチ命令の履歴に従ってブランチするかどうかを判断する動的ブランチ予測処理を採用した。本報告ではパイプライン処理方式の例として8種類のパイプラインモデルを考え、「エラトステネスのふるい」のベンチマークプログラムに対して各種モデルにおける動的ブランチ予測処理の効果をシミュレーションにより検討した結果について報告する。本報告のシミュレーションではパイプライン段数が4段以上の場合に動的ブランチ処理により10％前後の性能向上が見られた。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Pipelining is one of the most efficient techniques to reach higher performance. A fundamental disadvantage of pipelining is the performance degradation from branches in the instruction stream. The architecture of our microprocessor is newly developed and it is different from old pipelined computers. So, we designed several types of pipelining models for our microprocessor and examined their performance. We designed a branch prediction mechanism based on branch history to overcome this problem. Improvements of 5 to 14 percent can be expected in our microprocessor performance when we install this branch prediction mechanism.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"10","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告計算機アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"1987-03-13","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"20(1986-ARC-044)","bibliographicVolumeNumber":"1987"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":24881,"updated":"2025-01-22T19:43:24.887633+00:00","links":{},"created":"2025-01-18T22:55:54.352807+00:00"}