{"updated":"2025-01-22T19:44:58.000424+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00024831","sets":["1164:1579:1726:1737"]},"path":["1737"],"owner":"1","recid":"24831","title":["Prolog指向RISCプロセッサ“Pegasus”　－プロトタイプ開発とその評価－"],"pubdate":{"attribute_name":"公開日","attribute_value":"1988-01-21"},"_buckets":{"deposit":"4e753e9e-40b5-417e-b477-89d3b2bd3d0e"},"_deposit":{"id":"24831","pid":{"type":"depid","value":"24831","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"Prolog指向RISCプロセッサ“Pegasus”　－プロトタイプ開発とその評価－","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Prolog指向RISCプロセッサ“Pegasus”　－プロトタイプ開発とその評価－"},{"subitem_title":"A PROLOG - ORIENTED RISC PROCESSOR \"PEGASUS\" -PROTOTYPING AND ITS EVALUATION-","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1988-01-21","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"三菱電機株式会社中央研究所"},{"subitem_text_value":"三菱電機株式会社中央研究所"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Central Research Laboratory Mitsubishi Electric Corporation","subitem_text_language":"en"},{"subitem_text_value":"Central Research Laboratory Mitsubishi Electric Corporation","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/24831/files/IPSJ-ARC87048011.pdf"},"date":[{"dateType":"Available","dateValue":"1990-01-21"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC87048011.pdf","filesize":[{"value":"1.3 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"188289ac-2709-4972-beb5-0e89bb3a2fad","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1988 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"瀬尾, 和男"},{"creatorName":"横田, 隆史"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Kazuo, Seo","creatorNameLang":"en"},{"creatorName":"Takashi, Yokota","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"我々の研究所において開発を進めているRISC方弐μプロセッサ\"Pegasus\"は、カスタムVLSI技術に基づくProlog処理の高速化を目指したものであり、Prologの実行形態に即したスタック操作、タグ操作、Backtrackに伴う状態の退避・復旧等を効率良く実行できる命令セットを備えている。特に、Backtrackに伴う状態の退避・復旧に関しては、互いにコピー可能なレジスタ対によって構成されるレジスタ・ファイルをカスタムVLSI設計によって実現し、高速化を図っている。本報告では、Pegasusアーキテクチャを検証する目的で行ったプロトタイプ・チップの開発について述べる。このチップは、プロトタイプ開発に要する時間の短縮化を目標にフルカスタム／スタンダード・セル方式によって設計されている。テスト・ボードに組み込んだ試験の結果、マシンサイクル200nsで動作可能であり、Append:239KLIPS、Quicksort:149KLIPSの推論性能を達成している。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Pegasus is a Prolog-oriented RISC processor. By making the best use of custom VLSI technology, it provides an efficient way of performing Prolog-oriented operations. The cost of backtracking especially is reduced by the use of a register-file partially composed of register pairs which can be copied into each other. This report presents the development of a prototype Pegasus chip which has a processing speed of 239KLIPS (Kilo Logical Inferences Per Second) for a deterministic append program and 149KLIPS for a non-deterministic quicksort program.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"88","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告計算機アーキテクチャ（ARC）"}],"bibliographicPageStart":"81","bibliographicIssueDates":{"bibliographicIssueDate":"1988-01-21","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"4(1987-ARC-048)","bibliographicVolumeNumber":"1988"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"created":"2025-01-18T22:55:52.026336+00:00","id":24831,"links":{}}