{"links":{},"id":24709,"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00024709","sets":["1164:1579:1714:1718"]},"path":["1718"],"owner":"1","recid":"24709","title":["並列計算機テストベットATTEMPTの実装と評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"1989-09-19"},"_buckets":{"deposit":"7529d43e-a4f5-493d-a77e-d507b630375c"},"_deposit":{"id":"24709","pid":{"type":"depid","value":"24709","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"並列計算機テストベットATTEMPTの実装と評価","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"並列計算機テストベットATTEMPTの実装と評価"},{"subitem_title":"The implementation and performance estimation of a multiprocessor test - bed ATTEMPT","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1989-09-19","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"慶應義塾大学理工学部"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Faculty of Science and Technology, KEIO University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/24709/files/IPSJ-ARC89078004.pdf"},"date":[{"dateType":"Available","dateValue":"1991-09-19"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC89078004.pdf","filesize":[{"value":"807.0 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"c41f962d-21e1-45f9-9846-d038e510631d","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1989 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"天野, 英晴"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Hideharu, Amano","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"並列計算機テストベットATTEMPTは最大20台のプロセッサから成る小規模バス結合型マルチプロセッサである。そのアーキテクチャは、統合設計された同期機構とキャッシュを持ち、バスにはIEEE Futurebusを用いている点に特徴がある。本報告では現在稼働中のATTEMPTOのハードウェア構成について述べ、同期機構とFuturebusインタフェースの性能評価を行う。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"The multiprocessor test-bed ATTEMPT is a small scale bus-connected multiprocessor which consists of 20 processors. The communication mechanism of ATTEMPT is designed based on a concept of \"Cache with Synchronization Mechanism\", which provides powerful support for various kinds of communications in multiprocessors using IEEE Futurebus. The implemenation of the prototype called ATTEMPTO is described, and the performance of its communication mechanism is briefly estimated.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"8","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告計算機アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"1989-09-19","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"74(1989-ARC-078)","bibliographicVolumeNumber":"1989"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"created":"2025-01-18T22:55:46.644956+00:00","updated":"2025-01-22T19:48:00.111026+00:00"}