{"links":{},"id":24681,"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00024681","sets":["1164:1579:1701:1713"]},"path":["1713"],"owner":"1","recid":"24681","title":["CAMを用いた機能メモリ型並列プロセサFMPP"],"pubdate":{"attribute_name":"公開日","attribute_value":"1990-01-25"},"_buckets":{"deposit":"86b284ad-253e-41f0-87fb-9a124935c8fc"},"_deposit":{"id":"24681","pid":{"type":"depid","value":"24681","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"CAMを用いた機能メモリ型並列プロセサFMPP","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"CAMを用いた機能メモリ型並列プロセサFMPP"},{"subitem_title":"Functional Memory type Parallel Processor Architecture Based on CAM : FMPP","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1990-01-25","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"京都大学工学部"},{"subitem_text_value":"京都大学工学部"},{"subitem_text_value":"京都大学工学部"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Department of Electronics, Faculty of Engineering Kyoto University","subitem_text_language":"en"},{"subitem_text_value":"Department of Electronics, Faculty of Engineering Kyoto University","subitem_text_language":"en"},{"subitem_text_value":"Department of Electronics, Faculty of Engineering Kyoto University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/24681/files/IPSJ-ARC89080012.pdf"},"date":[{"dateType":"Available","dateValue":"1992-01-25"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC89080012.pdf","filesize":[{"value":"1.2 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"77644cf5-ce87-452b-b64d-6f8f6566d44e","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1990 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"辻本, 泰造"},{"creatorName":"安浦, 寛人"},{"creatorName":"田丸, 啓吉"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Taizo, Tsujimoto","creatorNameLang":"en"},{"creatorName":"Hiroto, Yasuura","creatorNameLang":"en"},{"creatorName":"Keikichi, Tamaru","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"機能メモリの各語を一つのプロセサと見なすことで，メモリ集積回路技術の進歩をそのまま大規模な超並列計算機構の実現に利用することができる．われわれは，このような並列アーキテクチャを機能メモリ型並列プロセサアーキテクチャFMPPと呼ぶ．本報告では，代表的な機能メモリであるCAM(Contents Addressable Memory)を基本にしたFMPPアーキテクチャを提案する．メモリの各語は1ビットのプロセサとして働き，システム全体では語数分の並列度を持ったSIMDマシンとなる．ここでは，このアーキテクチャの上での主な基本演算の計算時間の評価を行なうとともに，応用例を示す．現在の集積回路技術で，数百万プロセサが実現できると考えられる．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"We have been investigating a parallel processor architecture using functional memories, called FMPP (Functional Memory type Parallel Processor architecture). In this report, we show an FMPP architecture based on CAM (Contents Addressable Memory). Each word of the memory is a processor unit performing a bit serial computation. The architecture is a kind of SIMD, and the number of processors can be increased rapidly according the progress of memory LSI technology. More than millions of processors will be implemented by the recent technology. We show application fields of the FMPP architecture and evaluate algorithms for basic operations on the architecture.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"96","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告計算機アーキテクチャ（ARC）"}],"bibliographicPageStart":"89","bibliographicIssueDates":{"bibliographicIssueDate":"1990-01-25","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"7(1989-ARC-080)","bibliographicVolumeNumber":"1990"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"created":"2025-01-18T22:55:45.400835+00:00","updated":"2025-01-22T19:48:54.942290+00:00"}