{"links":{},"id":24638,"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00024638","sets":["1164:1579:1701:1706"]},"path":["1706"],"owner":"1","recid":"24638","title":["高並列計算機CAP - IIのメッセージコントローラ"],"pubdate":{"attribute_name":"公開日","attribute_value":"1990-07-18"},"_buckets":{"deposit":"d092a5cb-ef9c-453e-8700-4bf2a07a19cc"},"_deposit":{"id":"24638","pid":{"type":"depid","value":"24638","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"高並列計算機CAP - IIのメッセージコントローラ","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"高並列計算機CAP - IIのメッセージコントローラ"},{"subitem_title":"A Message Controller for a Highly Parallel Processor, CAP - II","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1990-07-18","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"（株）富士通研究所"},{"subitem_text_value":"（株）富士通研究所"},{"subitem_text_value":"（株）富士通研究所"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Fujitsu Laboratories LTD.","subitem_text_language":"en"},{"subitem_text_value":"Fujitsu Laboratories LTD.","subitem_text_language":"en"},{"subitem_text_value":"Fujitsu Laboratories LTD.","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/24638/files/IPSJ-ARC90083040.pdf"},"date":[{"dateType":"Available","dateValue":"1992-07-18"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC90083040.pdf","filesize":[{"value":"881.5 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"8239c100-1d83-41c8-b79f-481857a8284c","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1990 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"清水, 俊幸"},{"creatorName":"石畑, 宏明"},{"creatorName":"堀江, 健志"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Toshiyuki, Shimizu","creatorNameLang":"en"},{"creatorName":"Hiroaki, Ishihata","creatorNameLang":"en"},{"creatorName":"Takeshi, Horie","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"高並列計算機CAP?IIのプロセッサエレメント（セル）を構成するマイクロプロセッサ(ARC?)とキャッシュメモリ，大容量メモリ，I/OデバイスをインタフェースするLSI，メッセージコントローラ(）を開発した．数値シミュレーションや映像生成を対象としたCAP?IIの特徴を踏まえ，通信デバイスの転送能力にあった十分な量のデータをセルの計算能力を損なうことなく供給できるようにした．MSCには，キャッシュコントローラも集積するため，その動作情報を利用したメッセージ送信（ラインセンド）も実現した．本報告では，MSCが提供するこれらの機能について述べる．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"We developed a message controller (MSC) for a highly parallel processor, CAP-II. The MSC realize interface among a microprocessor (SPARC-IU), cache memories, dynamic RAM modules and I/O devices. It is designed to supply enough data to I/O devices without penalties to calculation. Its design is based on CAP-II architecture, which handles image generations and numerical simulations. A cache controller, which is also incorporated in the MSC, makes it possible to execute a special message transfer (line send). We present the architecture and performance of the MSC.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"240","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告計算機アーキテクチャ（ARC）"}],"bibliographicPageStart":"235","bibliographicIssueDates":{"bibliographicIssueDate":"1990-07-18","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"60(1990-ARC-083)","bibliographicVolumeNumber":"1990"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"created":"2025-01-18T22:55:43.489708+00:00","updated":"2025-01-22T19:51:02.622317+00:00"}