{"links":{},"id":24635,"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00024635","sets":["1164:1579:1701:1706"]},"path":["1706"],"owner":"1","recid":"24635","title":["高並列計算機CAP - IIの構成とメモリシステム"],"pubdate":{"attribute_name":"公開日","attribute_value":"1990-07-18"},"_buckets":{"deposit":"f3f71fb0-d807-437b-8ab8-367457e47258"},"_deposit":{"id":"24635","pid":{"type":"depid","value":"24635","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"高並列計算機CAP - IIの構成とメモリシステム","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"高並列計算機CAP - IIの構成とメモリシステム"},{"subitem_title":"An Architecture of Highly Parallel Processor CAP - II","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1990-07-18","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"（株）富士通研究所"},{"subitem_text_value":"（株）富士通研究所"},{"subitem_text_value":"（株）富士通研究所"},{"subitem_text_value":"（株）富士通研究所"},{"subitem_text_value":"（株）富士通研究所"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"FUJITSU LABORATORIES LTD.","subitem_text_language":"en"},{"subitem_text_value":"FUJITSU LABORATORIES LTD.","subitem_text_language":"en"},{"subitem_text_value":"FUJITSU LABORATORIES LTD.","subitem_text_language":"en"},{"subitem_text_value":"FUJITSU LABORATORIES LTD.","subitem_text_language":"en"},{"subitem_text_value":"FUJITSU LABORATORIES LTD.","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/24635/files/IPSJ-ARC90083037.pdf"},"date":[{"dateType":"Available","dateValue":"1992-07-18"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC90083037.pdf","filesize":[{"value":"966.1 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"6b115062-54d0-4ccf-b533-db0be57a0692","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1990 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"石畑, 宏明"},{"creatorName":"稲野, 聡"},{"creatorName":"堀江, 健志"},{"creatorName":"清水, 俊幸"},{"creatorName":"加藤, 定幸"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Hiroaki, Ishihata","creatorNameLang":"en"},{"creatorName":"Satoshi, Inano","creatorNameLang":"en"},{"creatorName":"Takeshi, Horie","creatorNameLang":"en"},{"creatorName":"Toshiyuki, Shimizu","creatorNameLang":"en"},{"creatorName":"Sadayuki, Kato","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"プロセッサエレメントのメモリシステムの構成について述べる．CAP?IIは，64?1024台のプロセッサ・エレメントからなる分散メモリ型の並列計算機である．並列計算機をさまざまなアプリケーションに適用するためには，高い単体プロセッサの演算性能と，高速なプロセッサ間通信が要求される．CAP?IIでは，プロセッサに32ビットRISCマイクロプロセッサを採用し，用途別の3種類のネットワークを持つことにより高性能を実現する．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In this paper, we present an architecture of CAP-II. CAP-II is a highly parallel processor consists of 64 to 1024 processing elements (PEs). Highly parallel processor must have both powerful PEs and high speed communication network to achieve high performance in variety of problems. We use 32bit RISC micro-processor with cache memory for PE. And the system has 3 different type networks for broadcast, 10calcommunication, and synchronization.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"222","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告計算機アーキテクチャ（ARC）"}],"bibliographicPageStart":"217","bibliographicIssueDates":{"bibliographicIssueDate":"1990-07-18","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"60(1990-ARC-083)","bibliographicVolumeNumber":"1990"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"created":"2025-01-18T22:55:43.357208+00:00","updated":"2025-01-22T19:50:53.791776+00:00"}